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Shabbir H. Batterywala
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2010 – 2019
- 2015
- [c17]Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala:
2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids. VLSID 2015: 186-191 - 2014
- [c16]Sambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir H. Batterywala:
Fixing Double Patterning violations with look-ahead. ASP-DAC 2014: 149-154 - 2013
- [c15]Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala:
Automatic design rule correction in presence of multiple grids and track patterns. DAC 2013: 26:1-26:6
2000 – 2009
- 2009
- [c14]Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala:
Efficient Analog/RF Layout Closure with Compaction Based Legalization. VLSI Design 2009: 137-142 - 2008
- [c13]Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy:
On Efficient and Robust Constraint Generation for Practical Layout Legalization. ISQED 2008: 379-384 - [c12]Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy:
Cell Swapping Based Migration Methodology for Analog and Custom Layouts. ISQED 2008: 450-455 - 2007
- [c11]Subramanian Rajagopalan, Shabbir H. Batterywala:
A 3-dimensional FEM Based Resistance Extraction. VLSI Design 2007: 565-570 - [c10]Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou:
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880 - 2006
- [c9]Shabbir H. Batterywala, Rohit Ananthakrishna, Yansheng Luo, Alex Gyure:
A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills. VLSI Design 2006: 129-134 - [c8]Rohit Ananthakrishna, Shabbir H. Batterywala:
MoM - A Process Variation Aware Statistical Capacitance Extractor. VLSI Design 2006: 135-140 - 2005
- [c7]Shabbir H. Batterywala, Madhav P. Desai:
Variance Reduction in Monte Carlo Capacitance Extraction. VLSI Design 2005: 85-90 - 2004
- [c6]Shabbir H. Batterywala, Narendra V. Shenoy:
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. VLSI Design 2004: 989-994 - 2003
- [c5]Shabbir H. Batterywala, Narendra V. Shenoy:
A Method to Estimate Slew and Delay in Coupled Digital Circuits. VLSI Design 2003: 411-416 - 2002
- [c4]Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou:
Track assignment: a desirable intermediate step between global routing and detailed routing. ICCAD 2002: 59-66 - 2001
- [c3]Shabbir H. Batterywala, H. Narayanan:
Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports. VLSI Design 2001: 500-
1990 – 1999
- 1999
- [c2]Shabbir H. Batterywala, H. Narayanan:
Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks. VLSI Design 1999: 169-174 - 1997
- [c1]Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan:
A New Partitioning Strategy Based on Supermodular Functions. VLSI Design 1997: 32-37
Coauthor Index
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