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Chan-Hsiang Weng
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2010 – 2019
- 2019
- [c7]Tien-Yu Lo, Chan-Hsiang Weng, Hung-Yi Hsieh, Yun-Shiang Shu, Pao-Cheng Chiu:
An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS. ISSCC 2019: 334-336 - [c6]Chan-Hsiang Weng, Tzu-An Wei, Hung-Yi Hsieh, Su-Hao Wu, Ting-Yang Wang:
A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS. VLSI Circuits 2019: 228- - 2017
- [j5]Chan-Hsiang Weng, Yung-Yu Lin, Tsung-Hsien Lin
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A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1085-1093 (2017) - 2016
- [j4]Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, Tsung-Hsien Lin
A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer. IEEE J. Solid State Circuits 51(5): 1235-1245 (2016) - 2015
- [j3]Chan-Hsiang Weng
A CMOS Thermistor-Embedded Continuous-Time Delta-Sigma Temperature Sensor With a Resolution FoM of 0.65 pJ°C2. IEEE J. Solid State Circuits 50(11): 2491-2500 (2015) - [c5]Chan-Hsiang Weng, Wei-Hsiang Huang, Erkan Alpman, Tsung-Hsien Lin
A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS. A-SSCC 2015: 1-4 - [c4]Chan-Hsiang Weng, Tzu-An Wei, Tsung-Hsien Lin
A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizer. VLSI-DAT 2015: 1-4 - 2014
- [j2]Chen-Chien Lin, Chan-Hsiang Weng, Tzu-An Wei, Yung-Yu Lin, Tsung-Hsien Lin
A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta-Sigma Modulator. IEEE Trans. Circuits Syst. II Express Briefs 61-II(2): 75-79 (2014) - [c3]Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin
A CMOS thermistor-embedded continuous-time delta-sigma temperature sensor with a resolution of 0.01 °C. A-SSCC 2014: 149-152 - [c2]Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, Yi-Ting Tseng, Tsung-Hsien Lin
An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS. VLSIC 2014: 1-2 - 2013
- [c1]Chen-Chien Lin, Chan-Hsiang Weng, Tsung-Hsien Lin
A low-power dual-mode continuous-time delta-sigma modulator with a folded quantizer. VLSI-DAT 2013: 1-4 - 2011
- [j1]Chan-Hsiang Weng, Chen-Chien Lin, Yu-Cheng Chang, Tsung-Hsien Lin
A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation. IEEE Trans. Circuits Syst. II Express Briefs 58-II(12): 867-871 (2011)
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