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Gopalakrishnan Lakshminarayanan
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- affiliation: National Institute of Technology, Department of Electronics and Communication Engineering, Tiruchirappalli, India
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2020 – today
- 2024
- [j33]T. S. Manivannan
, K. R. Pasupathy, Mohd Rizwan Uddin Shaikh
Optimization of DE-QG TFET using novel CIP and DCT techniques. Microelectron. J. 144: 106097 (2024) - [j32]T. S. Manivannan
Ambipolar current suppression in drain elevated TFET using a novel extended drain structure with a moderate doping profile. Microelectron. J. 151: 106302 (2024) - [c16]Muhammed Raees P. C, Akshayraj M. R, Varun P. Gopi, G. Lakshminarayanan, G. R. Gangadharan, Jayaraj U. Kidav:
Dynamic Precision Scaling in MAC Units for Energy-Efficient Computations in Deep Neural Network Accelerators. VDAT 2024: 1-7 - [c15]Akshayraj M. R, Muhammed Raees P. C, Varun P. Gopi, G. Lakshminarayanan, G. R. Gangadharan, Jayaraj U. Kidav:
Energy-Efficient Hardware Design for CNN-Based ECG Signal Classification in Wearable Bio-Medical Devices. VDAT 2024: 1-7 - 2023
- [j31]Raja Sekar Kumaresan
Framework for QCA Layout Generation and Rules for Rotated Cell Design. J. Circuits Syst. Comput. 32(7): 2350114:1-2350114:14 (2023) - [j30]Aravindhan Alagarsamy
SaHNoC: an optimal energy efficient hybrid networks-on-chip architecture. J. Supercomput. 79(6): 6538-6559 (2023) - 2022
- [j29]Marshal Raj
Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata. IEEE Des. Test 39(5): 88-97 (2022) - [j28]Raja Sekar Kumaresan
High-Speed Serial-Parallel Multiplier in Quantum-Dot Cellular Automata. IEEE Embed. Syst. Lett. 14(1): 31-34 (2022) - [j27]Aravindhan Alagarsamy
FRDS: An efficient unique on-Chip interconnection network architecture. Integr. 87: 90-103 (2022) - [j26]Utkarsh Tiwari
Secure and Energy Efficient Design of Multi-Modular Exponential Techniques for Public-Key Cryptosystem. J. Commun. Inf. Networks 7(3): 309-323 (2022) - [j25]Aravindhan Alagarsamy
SMA: A constructive partitioning based mapping approach for Networks-on-Chip. Microprocess. Microsystems 94: 104678 (2022) - [j24]Parameshwaran Ramalingam, R. Thanuja, R. Bhavani, Gopalakrishnan Lakshminarayanan:
An Efficient Lossless Telemetry Data Compression and Fault Analysis System Using 2SMLZ and CMOW-DLNN. Wirel. Pers. Commun. 127(3): 2325-2345 (2022) - [c14]Anantharaj Thalaimalai Vanaraj
Optimal Test Sequences for Logic Verification closure in State Dependent RTL Digital designs. ICCCNT 2022: 1-6 - [c13]Anantharaj Thalaimalai Vanaraj
Reliable Quantum-dot Cellular Automata Coplanar Adder and Subtractor for Multi-bit Designs. ICCCNT 2022: 1-4 - 2021
- [j23]J. Sujanth Roy
High-Speed Architecture for Successive Cancellation Decoder With Split-g Node Block. IEEE Embed. Syst. Lett. 13(3): 118-121 (2021) - [j22]Parameshwaran Ramalingam, Gopalakrishnan Lakshminarayanan, Manikandan Ramachandran, Rizwan Patan:
Kinematic adaptive frequency sampling combined spatio temporal features for snow monitoring in aerospace applications. Expert Syst. Appl. 184: 115472 (2021) - [j21]Marshal Raj
Reliable SRAM using NAND-NOR Gate in beyond-CMOS QCA technology. IET Comput. Digit. Tech. 15(3): 202-213 (2021) - [j20]Bibin Sam Paul S, Antony Xavier Glittas
A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition. Integr. 76: 69-75 (2021) - [j19]R. Umamaheswaran, Parameshwaran Ramalingam, Marshal Raj
A novel boundary elemental analysis based frequency domain adaptive sampling technique for aerospace application. Microprocess. Microsystems 83: 103506 (2021) - [j18]Mohammadreza Asadikouhanjani
A Real-Time Architecture for Pruning the Effectual Computations in Deep Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 2030-2041 (2021) - 2020
- [j17]Marshal Raj
Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems. IEEE Embed. Syst. Lett. 12(4): 113-116 (2020) - [c12]Raja Sekar Kumaresan
Area-Efficient D-Flip Flop and XOR in QCA. ICCCNT 2020: 1-5
2010 – 2019
- 2019
- [j16]Aravindhan Alagarsamy
A Self-Adaptive Mapping Approach for Network on Chip With Low Power Consumption. IEEE Access 7: 84066-84081 (2019) - [j15]Aravindhan Alagarsamy
KBMA: A knowledge-based multi-objective application mapping approach for 3D NoC. IET Comput. Digit. Tech. 13(4): 324-334 (2019) - [j14]Geethu Sathees Babu, Lakshmi Renuka Madala, Gopalakrishnan Lakshminarayanan
Low-complex processing element architecture for successive cancellation decoder. Integr. 66: 80-87 (2019) - [j13]Geethu Sathees Babu, Gopalakrishnan Lakshminarayanan
Reconfigurable address generator for multi-standard interleaver. Microprocess. Microsystems 65: 47-56 (2019) - [c11]Marshal Raj
High Speed Controllable Inverter for Adder-Subtractor in QCA. ICCCNT 2019: 1-5 - [c10]Marshal Raj
Optimized Multiplexer and Exor gate in 4-dot 2-electron QCA using Novel Input Technique. ICCCNT 2019: 1-4 - 2018
- [c9]Kartikeya Dubey, Marshal Raj
Design of Majority Logic Based Comparator. ICCCNT 2018: 1-6 - 2016
- [j12]Antony Xavier Glittas
Two-parallel pipelined fast Fourier transform processors for real-valued signals. IET Circuits Devices Syst. 10(4): 330-336 (2016) - [j11]Nithish Kumar Venkatachalam
Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios. IET Comput. Digit. Tech. 10(2): 59-68 (2016) - [j10]Antony Xavier Glittas
A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2402-2406 (2016) - 2015
- [j9]Venkatachalam Nithish Kumar
An Improved Reconfigurable Finite Impulse Response Filter Using Common Subexpression Elimination Algorithm for Cognitive Radio. J. Low Power Electron. 11(2): 181-189 (2015) - 2014
- [j8]K. Swaminathan, G. Lakshminarayanan
Design and verification of an efficient WISHBONE-based network interface for network on chip. Comput. Electr. Eng. 40(6): 1838-1857 (2014) - [j7]Venkatachalam Nithish Kumar
Low Power and Area Efficient Carry Select Adder. J. Low Power Electron. 10(4): 593-601 (2014) - [c8]Sandeep Gopi Nambiar, K. Swaminathan, G. Lakshminarayanan
QaMC - QoS Aware Multicast router for NoC fabric. CCECE 2014: 1-6 - [c7]K. Swaminathan, Sandeep Gopi Nambiar, Rajkumar, G. Lakshminarayanan
A novel hybrid topology for Network on Chip. CCECE 2014: 1-6 - [c6]Antony Xavier Glittas
Pipelined FFT architectures for real-time signal processing and wireless communication applications. VDAT 2014: 1-2 - 2013
- [j6]C. Vennila
Dynamic partial reconfigurable Viterbi decoder for wireless standards. Comput. Electr. Eng. 39(2): 164-174 (2013) - [j5]K. Swaminathan, G. Lakshminarayanan
High Speed Low Power Ping Pong Buffering Based Network Interface for Network on Chip. J. Low Power Electron. 9(3): 322-331 (2013) - [c5]K. Swaminathan, G. Lakshminarayanan
Design of a low power network interface for Network on chip. CCECE 2013: 1-4 - [c4]C. Vennila
Dynamic partial reconfigurable adaptive transceiver for OFDM based cognitive radio. CCECE 2013: 1-4 - 2012
- [j4]C. Vennila
Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems. Circuits Syst. Signal Process. 31(3): 1049-1066 (2012) - [c3]C. Vennila
Dynamic partial reconfigurable FFT/IFFT pruning for OFDM based Cognitive radio. ISCAS 2012: 33-36 - [c2]K. Swaminathan, G. Lakshminarayanan
High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers. ISED 2012: 72-76 - [c1]Deepa N. Sarma, Gopalakrishnan Lakshminarayanan
A Novel Encoding Scheme for Low Power in Network on Chip Links. VLSI Design 2012: 257-261
2000 – 2009
- 2008
- [j3]G. Seetharaman, B. Venkataramani, Gopalakrishnan Lakshminarayanan
Automation techniques for implementation of hybrid wave-pipelined 2D DWT. J. Real Time Image Process. 3(3): 217-229 (2008) - [j2]Gopalakrishnan Seetharaman, Balasubramanian Venkataramani, Gopalakrishnan Lakshminarayanan
VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme. VLSI Design 2008: 512746:1-512746:8 (2008) - 2005
- [j1]Gopalakrishnan Lakshminarayanan
Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 783-793 (2005)
Coauthor Index
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