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Youngil Lim
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2020 – today
- 2021
- [j1]Chang-Kyo Lee
, Hyung-Joon Chi, Jin-Seok Heo, Junghwan Park, Jin-Hun Jang, Dongkeon Lee, Jaehoon Jung, Dong-Hun Lee, Dae-Hyun Kim
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. IEEE J. Solid State Circuits 56(1): 212-224 (2021) - 2020
- [c2]Hyung-Joon Chi, Chang-Kyo Lee, Junghwan Park, Jin-Seok Heo, Jaehoon Jung, Dongkeon Lee, Dae-Hyun Kim
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. ISSCC 2020: 382-384
2000 – 2009
- 2005
- [c1]Youngho Lee, Dahee Kim, Youngil Lim, Kyuhyung Kim, Hae Sun Kim, Woontack Woo
Dream of Mee-Luck: Aspiration for a New Dawn. International Conference on Virtual Storytelling 2005: 280-283
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last updated on 2024-04-25 05:48 CEST by the dblp team
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