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John Poulton
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- affiliation: NVIDIA Inc., Durham, NC, USA
- affiliation (1980): PhD University of North Carolina, Chapel Hill, NC, USA
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2020 – today
- 2024
- [j16]Yoshinori Nishi
, John W. Poulton
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. IEEE J. Solid State Circuits 59(4): 1146-1157 (2024) - [c27]Walker J. Turner, John W. Poulton, Yoshinori Nishi, Xi Chen, Brian Zimmer, Sanquan Song, John M. Wilson, William J. Dally, C. Thomas Gray:
Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. CICC 2024: 1-7 - 2023
- [j15]Yoshinori Nishi
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. IEEE J. Solid State Circuits 58(4): 1062-1073 (2023) - [c26]Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c25]Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. VLSI Technology and Circuits 2022: 154-155 - 2020
- [c24]Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson, C. Thomas Gray:
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. ISSCC 2020: 126-128
2010 – 2019
- 2019
- [j14]John W. Poulton, John M. Wilson
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. IEEE J. Solid State Circuits 54(1): 43-54 (2019) - [c23]Xi Chen, Sanquan Song, John Poulton, Nikola Nedovic, Brian Zimmer, Stephen G. Tell, C. Thomas Gray:
Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET. CICC 2019: 1-4 - [c22]Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally:
A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. CICC 2019: 1-4 - 2018
- [c21]Sudhir S. Kudva, Sanquan Song, John W. Poulton, John M. Wilson, Wenxu Zhao, C. Thomas Gray:
A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module. CICC 2018: 1-4 - [c20]Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray:
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. CICC 2018: 1-8 - [c19]John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally:
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. ISSCC 2018: 276-278 - [c18]William J. Dally, C. Thomas Gray, John Poulton, Brucek Khailany, John M. Wilson, Larry R. Dennison:
Hardware-Enabled Artificial Intelligence. VLSI Circuits 2018: 3-6 - 2017
- [c17]Arijit Banerjee
A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors. CICC 2017: 1-4 - [c16]Laura Fick, Dennis Sylvester, John W. Poulton, John M. Wilson, C. Thomas Gray:
A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers. ISCAS 2017: 1-4 - 2016
- [j13]Mahmut E. Sinangil, John W. Poulton, Matthew R. Fojtik, Thomas H. Greer, Stephen G. Tell, Andreas J. Gotterba, Jesse Wang, Jason Golbus, Brian Zimmer, William J. Dally, C. Thomas Gray:
A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. IEEE J. Solid State Circuits 51(2): 557-567 (2016) - [c15]John M. Wilson, Matthew R. Fojtik, John W. Poulton, Xi Chen, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally:
8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. ISSCC 2016: 156-157 - 2014
- [c14]Arijit Banerjee
A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs. ISQED 2014: 1-8 - 2013
- [j12]John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, John M. Wilson, C. Thomas Gray:
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications. IEEE J. Solid State Circuits 48(12): 3206-3218 (2013) - [c13]John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, C. Thomas Gray:
A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications. ISSCC 2013: 404-405 - 2010
- [j11]Brian S. Leibowitz, Robert Palmer, John Poulton, Yohan Frans, Simon Li, John M. Wilson, Michael Bucher, Andrew M. Fuller, John G. Eyles, Marko Aleksic, Trey Greer, Nhat Nguyen:
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling. IEEE J. Solid State Circuits 45(4): 889-898 (2010)
2000 – 2009
- 2007
- [j10]John Poulton, Robert Palmer, Andrew M. Fuller, Trey Greer, John G. Eyles, William J. Dally, Mark Horowitz:
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS. IEEE J. Solid State Circuits 42(12): 2745-2757 (2007) - [c12]Robert Palmer, John Poulton, William J. Dally, John G. Eyles, Andrew M. Fuller, Trey Greer, Mark Horowitz, Mark Kellam, F. Quan, F. Zarkeshvari:
A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications. ISSCC 2007: 440-614 - 2006
- [j9]Mike Yun He, John Poulton:
A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver. IEEE J. Solid State Circuits 41(3): 597-606 (2006) - 2004
- [j8]Ramin Farjad-Rad, Anhtuyet Nguyen, James Tran, Trey Greer, John Poulton, William J. Dally, John H. Edmondson, Ramesh Senthinathan, Rohit Rathi, Ming-Ju Edward Lee, Hiok-Tiaq Ng:
A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. IEEE J. Solid State Circuits 39(9): 1553-1561 (2004) - [j7]Chris Dwyer, Leandra Vicci, John W. Poulton, Dorothy Erie
The design of DNA self-assembled computing circuitry. IEEE Trans. Very Large Scale Integr. Syst. 12(11): 1214-1220 (2004) - 2003
- [j6]Ming-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan:
Jitter transfer characteristics of delay-locked loops - theories and design techniques. IEEE J. Solid State Circuits 38(4): 614-621 (2003) - [j5]Hiok-Tiaq Ng, Ramin Farjad-Rad, Ming-Ju Edward Lee, William J. Dally, Trey Greer, John Poulton, John H. Edmondson, Rohit Rathi, Ramesh Senthinathan:
A second-order semidigital clock recovery circuit based on injection locking. IEEE J. Solid State Circuits 38(12): 2101-2110 (2003) - [c11]Hiok-Tiaq Ng, Ming-Ju Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran:
A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. CICC 2003: 77-80 - [c10]Ming-Ju Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton:
CMOS High-Speed I/Os - Present and Future. ICCD 2003: 454-461 - 2002
- [j4]Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton:
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. IEEE J. Solid State Circuits 37(12): 1804-1812 (2002) - 2001
- [b1]William J. Dally, John W. Poulton:
Digital systems engineering. Cambridge University Press 2001, ISBN 978-0-521-59292-5, pp. I-XXIV, 1-663
1990 – 1999
- 1999
- [c9]John Poulton:
Problems and Prospects for Electrical Signaling. ARVLSI 1999: 326- - 1998
- [j3]John Poulton, William J. Dally, Steve Tell:
A tracking clock recovery receiver for 4-Gbps signaling. IEEE Micro 18(1): 25-27 (1998) - 1997
- [j2]William J. Dally, John W. Poulton:
Transmitter equalization for 4-Gbps signaling. IEEE Micro 17(1): 48-56 (1997) - [c8]John Poulton:
An Embedded DRAM for CMOS ASICs. ARVLSI 1997: 288-302 - [c7]John G. Eyles, Steven Molnar, John Poulton, Trey Greer, Anselmo Lastra, Nick England, Lee Westover:
PixelFlow: The Realization. Workshop on Graphics Hardware 1997: 57-67 - 1992
- [j1]John Poulton, John G. Eyles, Steven E. Molnar, Henry Fuchs:
Breaking the frame-buffer bottleneck with logic-enhanced memories. IEEE Computer Graphics and Applications 12(6): 65-74 (1992) - [c6]Steven Molnar, John G. Eyles, John Poulton:
PixelFlow: high-speed rendering using image composition. SIGGRAPH 1992: 231-240
1980 – 1989
- 1989
- [c5]Henry Fuchs, John Poulton, John G. Eyles, Trey Greer, Jack Goldfeather, David A. Ellsworth, Steven Molnar, Greg Turk, Brice Tebbs, Laura Israel:
Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories. SIGGRAPH 1989: 79-88 - 1987
- [c4]John G. Eyles, John D. Austin, Henry Fuchs, Trey Greer, John Poulton:
Pixel-Planes 4: A Summary. Advances in Computer Graphics Hardware 1987: 183-207 - 1985
- [c3]Henry Fuchs, Jack Goldfeather, Jeff P. Hultquist, Susan Spach, John D. Austin, Frederick P. Brooks Jr., John G. Eyles, John Poulton:
Fast Spheres, Shadows, Textures, Transparencies, and Image Enhancements in Pixel-Planes. Advances in Computer Graphics 1985: 169-187 - [c2]Henry Fuchs, Jack Goldfeather, Jeff P. Hultquist, Susan Spach, John D. Austin, Frederick P. Brooks Jr., John G. Eyles, John Poulton:
Fast spheres, shadows, textures, transparencies, and imgage enhancements in pixel-planes. SIGGRAPH 1985: 111-120 - 1983
- [c1]Jonathan B. Rosenberg, David G. Boyer, John A. Dallen, Stephen W. Daniel, Charles J. Poirier, John Poulton, C. Durward Rogers, Neil Weste:
A vertically integrated VLSI design environment. DAC 1983: 31-38
Coauthor Index
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