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Florent de Dinechin
Florent Dupont de Dinechin
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2020 – today
- 2024
- [i3]Agathe Herrou, Florent de Dinechin, Stéphane Letz, Yann Orlarey, Anastasia Volkova:
Towards Fixed-Point Formats Determination for Faust Programs. CoRR abs/2403.06527 (2024) - 2023
- [c60]Anastasia Volkova, Rémi Garcia, Florent de Dinechin, Martin Kumm:
Hardware-Optimal Digital FIR Filters: One ILP to Rule Them all and in Faithfulness Bind Them. ACSSC 2023: 1574-1578 - [c59]Orégane Desrentes, Benoît Dupont de Dinechin, Florent de Dinechin:
Exact Fused Dot Product Add Operators. ARITH 2023: 151-158 - [c58]Maxime Popoff, Romain Michon, Tanguy Risset, Pierre Cochard, Stéphane Letz, Yann Orlarey, Florent de Dinechin:
Audio DSP to FPGA Compilation. ASAP 2023: 31-32 - 2022
- [j22]Paolo Montuschi, Jean-Michel Muller
, Florent de Dinechin
Computer Arithmetic: Continuing a Long and Steady Emergence. Computer 55(10): 4-6 (2022) - [j21]Maxime Christ
Lossless Differential Table Compression for Hardware Function Evaluation. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1642-1646 (2022) - [c57]Maxime Christ, Florent de Dinechin, Frédéric Pétrot:
Low-precision logarithmic arithmetic for neural network accelerators. ASAP 2022: 72-79 - [c56]Andreas Böttcher, Martin Kumm, Florent de Dinechin:
Resource Optimal Squarers for FPGAs. FPL 2022: 40-46 - [c55]Orégane Desrentes, Florent de Dinechin:
Using integer linear programming for correctly rounded multipartite architectures. FPT 2022: 1-8 - [c54]Luc Forget, Gauthier Harnisch, Ronan Keryell, Florent de Dinechin:
A single-source C++20 HLS flow for function evaluation on FPGA and beyond. HEART 2022: 51-58 - 2021
- [c53]Andreas Böttcher, Martin Kumm, Florent de Dinechin:
Resource Optimal Truncated Multipliers for FPGAs. ARITH 2021: 102-109 - [c52]Florent de Dinechin, Silviu-Ioan Filip, Martin Kumm, Anastasia Volkova:
Towards Arithmetic-Centered Filter Design. ARITH 2021: 115-118 - 2020
- [j20]Yohann Uguen
Application-Specific Arithmetic in High-Level Synthesis Tools. ACM Trans. Archit. Code Optim. 17(1): 5:1-5:23 (2020) - [c51]Andre Guntoro
Next Generation Arithmetic for Edge Computing. DATE 2020: 1357-1365
2010 – 2019
- 2019
- [j19]Anastasia Volkova
Towards Hardware IIR Filters Computing Just Right: Direct Form I Case Study. IEEE Trans. Computers 68(4): 597-608 (2019) - [j18]Javier D. Bruguera, Florent de Dinechin
Guest Editors Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 68(7): 951-952 (2019) - [c50]Andrea Bocco, Yves Durand, Florent de Dinechin:
Dynamic Precision Numerics Using a Variable-Precision UNUM Type I HW Coprocessor. ARITH 2019: 104-107 - [c49]Florent de Dinechin, Silviu-Ioan Filip, Martin Kumm, Luc Forget:
Table-Based versus Shift-And-Add Constant Multipliers for FPGAs. ARITH 2019: 151-158 - [c48]Florent de Dinechin:
Reflections on 10 Years of FloPoCo. ARITH 2019: 187-189 - [c47]Yohann Uguen, Luc Forget, Florent de Dinechin:
Evaluating the Hardware Cost of the Posit Number System. FPL 2019: 106-113 - [c46]Luc Forget, Yohann Uguen, Florent de Dinechin, David Thomas:
A type-safe arbitrary precision arithmetic portability layer for HLS tools. HEART 2019: 5:1-5:6 - [c45]Andrea Bocco, Tiago T. Jost, Albert Cohen, Florent de Dinechin, Yves Durand, Christian Fabre
Byte-Aware Floating-point Operations through a UNUM Computing Unit. VLSI-SoC 2019: 323-328 - 2018
- [b3]Jean-Michel Muller
Handbook of Floating-Point Arithmetic (2nd Ed.). Springer 2018, ISBN 978-3-319-76525-9 - [c44]Martin Kumm, Oscar Gustafsson
Karatsuba with Rectangular Multipliers for FPGAs. ARITH 2018: 13-20 - 2017
- [j17]Hatam Abdoli
Improving Energy Efficiency of OFDM Using Adaptive Precision Reconfigurable FFT. Circuits Syst. Signal Process. 36(7): 2742-2766 (2017) - [j16]H. Fatih Ugurdag
Hardware Division by Small Integer Constants. IEEE Trans. Computers 66(12): 2097-2110 (2017) - [c43]Matei Istoan, Florent de Dinechin:
Automating the pipeline of arithmetic datapaths. DATE 2017: 704-709 - [c42]Yohann Uguen, Florent de Dinechin, Steven Derrien:
A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators. FCCM 2017: 80 - [c41]Yohann Uguen, Florent de Dinechin, Steven Derrien:
Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations. FPL 2017: 1-8 - [e1]Neil Burgess, Javier D. Bruguera, Florent de Dinechin:
24th IEEE Symposium on Computer Arithmetic, ARITH 2017, London, United Kingdom, July 24-26, 2017. IEEE Computer Society 2017, ISBN 978-1-5386-1965-0 [contents] - 2016
- [c40]Julien Le Maire, Nicolas Brunie
Computing floating-point logarithms with fixed-point operations. ARITH 2016: 156-163 - 2015
- [c39]Florent de Dinechin, Matei Istoan:
Hardware Implementations of Fixed-Point Atan2. ARITH 2015: 34-41 - [c38]Nicolas Brunie
Code Generators for Mathematical Functions. ARITH 2015: 66-73 - 2014
- [c37]Florent de Dinechin, Matei Istoan, Abdelbassat Massouri:
Sum-of-product architectures computing just right. ASAP 2014: 41-47 - 2013
- [j15]Florent de Dinechin, Matei Istoan, Guillaume Sergent:
Fixed-point trigonometric functions on FPGAs. SIGARCH Comput. Archit. News 41(5): 83-88 (2013) - [j14]Florent de Dinechin, Christoph Quirin Lauter, Jean-Michel Muller
On Ziv's rounding test. ACM Trans. Math. Softw. 39(4): 25:1-25:19 (2013) - [j13]Florent de Dinechin, Pedro Echeverría, Marisa López-Vallejo
Floating-Point Exponentiation Units for Reconfigurable Computing. ACM Trans. Reconfigurable Technol. Syst. 6(1): 4:1-4:15 (2013) - [c36]Nicolas Brunie
Arithmetic core generation using bit heaps. FPL 2013: 1-8 - 2012
- [j12]Florent de Dinechin:
Multiplication by Rational Constants. IEEE Trans. Circuits Syst. II Express Briefs 59-II(2): 98-102 (2012) - [c35]Florent de Dinechin, Laurent-Stéphane Didier:
Table-Based Division by Small Integer Constants. ARC 2012: 53-63 - 2011
- [j11]Florent de Dinechin, Bogdan Pasca
Designing Custom Arithmetic Data Paths with FloPoCo. IEEE Des. Test Comput. 28(4): 18-27 (2011) - [j10]Florent de Dinechin, Christoph Quirin Lauter, Guillaume Melquiond
Certifying the Floating-Point Implementation of an Elementary Function Using Gappa. IEEE Trans. Computers 60(2): 242-253 (2011) - [c34]Nicolas Brunie
A mixed-precision fused multiply and add. ACSCC 2011: 165-169 - [c33]Florent de Dinechin:
The Arithmetic Operators You Will Never See in a Microprocessor. IEEE Symposium on Computer Arithmetic 2011: 189-190 - [c32]Florent de Dinechin, Jean-Michel Muller
An FPGA architecture for solving the Table Maker's Dilemma. ASAP 2011: 187-194 - 2010
- [b2]Jean-Michel Muller
Handbook of Floating-Point Arithmetic. Birkhäuser 2010, ISBN 978-0-8176-4704-9, pp. I-XXIII, 1-572 - [j9]Vincent Lefèvre, Philippe Théveny, Florent de Dinechin, Claude-Pierre Jeannerod, Christophe Mouilleron, David Pfannholzer, Nathalie Revol:
LEMA: towards a language for reliable arithmetic. ACM Commun. Comput. Algebra 44(1/2): 41-52 (2010) - [j8]Sebastian Banescu, Florent de Dinechin, Bogdan Pasca
Multipliers for floating-point double precision and beyond on FPGAs. SIGARCH Comput. Archit. News 38(4): 73-79 (2010) - [c31]Florent de Dinechin, Mioara Joldes, Bogdan Pasca
Automatic generation of polynomial-based hardware architectures for function evaluation. ASAP 2010: 216-222 - [c30]Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca
Pipelined FPGA Adders. FPL 2010: 422-427 - [c29]Florent de Dinechin, Mioara Joldes, Bogdan Pasca
Multiplicative Square Root Algorithms for FPGAs. FPL 2010: 574-577 - [c28]Florent de Dinechin, Bogdan Pasca
Floating-point exponential functions for DSP-enabled FPGAs. FPT 2010: 110-117 - [c27]Álvaro Vázquez, Florent de Dinechin:
Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs. FPT 2010: 126-133
2000 – 2009
- 2009
- [c26]Florent de Dinechin, Cristian Klein, Bogdan Pasca
Generating high-performance custom floating-point pipelines. FPL 2009: 59-64 - [c25]Florent de Dinechin, Bogdan Pasca
Large multipliers with fewer DSP blocks. FPL 2009: 250-255 - 2008
- [j7]Jérémie Detrey, Florent de Dinechin:
Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables. Tech. Sci. Informatiques 27(6): 673-698 (2008) - [c24]Nicolas Brisebarre, Florent de Dinechin, Jean-Michel Muller
Integer and floating-point constant multipliers for FPGAs. ASAP 2008: 239-244 - [c23]Ionut Trestian, Octavian Cret, Laura Cret, Lucia Vacariu, Radu Tudoran, Florent de Dinechin:
FPGA-Based Computation of the Inductance of Coils Used for the Magnetic Stimulation of the Nervous System. BIODEVICES (1) 2008: 151-155 - [c22]Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran:
When FPGAs are better at floating-point than microprocessors. FPGA 2008: 260 - [c21]Florent de Dinechin, Bogdan Pasca
An FPGA-specific approach to floating-point accumulation and sum-of-products. FPT 2008: 33-40 - [p1]Florent de Dinechin, Milos D. Ercegovac, Jean-Michel Muller, Nathalie Revol:
Digital Arithmetic. Wiley Encyclopedia of Computer Science and Engineering 2008 - [i2]Florent de Dinechin, Christoph Quirin Lauter, Guillaume Melquiond:
Certifying floating-point implementations using Gappa. CoRR abs/0801.0523 (2008) - [i1]Florent de Dinechin, Christoph Quirin Lauter:
Optimizing polynomials for floating-point implementation. CoRR abs/0803.0439 (2008) - 2007
- [b1]Florent de Dinechin:
Matériel et logiciel pour l'évaluation de fonctions numériques :précision, performance et validation. Claude Bernard University Lyon 1, France, 2007 - [j6]Florent de Dinechin, Christoph Quirin Lauter, Jean-Michel Muller
Fast and correctly rounded logarithms in double-precision. RAIRO Theor. Informatics Appl. 41(1): 85-102 (2007) - [j5]Jérémie Detrey, Florent de Dinechin:
Parameterized floating-point logarithm and exponential functions for FPGAs. Microprocess. Microsystems 31(8): 537-545 (2007) - [j4]Jérémie Detrey, Florent de Dinechin:
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic. J. VLSI Signal Process. 49(1): 161-175 (2007) - [c20]Jérémie Detrey, Florent de Dinechin, Xavier Pujol:
Return of the hardware floating-point elementary function. IEEE Symposium on Computer Arithmetic 2007: 161-168 - [c19]Jérémie Detrey, Florent de Dinechin:
Floating-Point Trigonometric Functions for FPGAs. FPL 2007: 29-34 - 2006
- [c18]Caroline Collange, Jérémie Detrey, Florent de Dinechin:
Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis. DSD 2006: 197-203 - [c17]Florent de Dinechin, Christoph Quirin Lauter, Guillaume Melquiond:
Assisted verification of elementary functions using Gappa. SAC 2006: 1318-1322 - 2005
- [j3]Florent de Dinechin, Arnaud Tisserand:
Multipartite Table Methods. IEEE Trans. Computers 54(3): 319-330 (2005) - [j2]Jérémie Detrey, Florent de Dinechin:
Outils pour une comparaison sans a priori entre arithmétique logarithmique et arithmétique flottante. Tech. Sci. Informatiques 24(6): 625-643 (2005) - [c16]Florent de Dinechin, Alexey V. Ershov, Nicolas Gast:
Towards the Post-Ultimate libm. IEEE Symposium on Computer Arithmetic 2005: 288-295 - [c15]Jérémie Detrey, Florent de Dinechin:
Table-based polynomials for fast hardware function evaluation. ASAP 2005: 328-333 - [c14]Jérémie Detrey, Florent de Dinechin:
A Parameterized Floating-Point Exponential Function for FPGAs. FPT 2005: 27-34 - 2004
- [c13]Jérémie Detrey, Florent de Dinechin:
Second Order Function Approximation Using a Single Multiplication on FPGAs. FPL 2004: 221-230 - 2003
- [c12]David Defour, Florent de Dinechin:
Software Carry-Save: A Case Study for Instruction-Level Parallelism. PaCT 2003: 207-214 - 2002
- [c11]Jérémie Detrey, Florent de Dinechin:
Multipartite Tables in JBits for the Evaluation of Functions on FPGAs. IPDPS 2002 - 2001
- [c10]Florent de Dinechin, Arnaud Tisserand:
Some Improvements on Multipartite Table Methods . IEEE Symposium on Computer Arithmetic 2001: 128-135 - 2000
- [j1]Florent de Dinechin:
The Price of Routing in FPGAs. J. Univers. Comput. Sci. 6(2): 227-239 (2000) - [c9]Florent de Dinechin, Vincent Lefèvre:
Constant Multipliers for FPGAs. PDPTA 2000
1990 – 1999
- 1999
- [c8]Florent de Dinechin, Wayne Luk, Steve McKeever:
Towards Adaptable Hierarchical Placement for FPGAs. FPGA 1999: 254 - 1998
- [c7]Wayne Luk, P. Andreou, Arran Derbyshire, Florent Dupont de Dinechin, J. Rice, Nabeel Shirazi, D. Siganos:
A Reconfigurable Engine for Real-Time Video Processing. FPL 1998: 169-178 - 1997
- [c6]Florent de Dinechin:
Libraries of schedule-free operators in Alpha. ASAP 1997: 239- - [c5]Florent de Dinechin, Tanguy Risset, Sophie Robert:
Hierarchical Static Analysis for Improving the Complexity of Linear Algebra Algorithms. PARCO 1997: 261-268 - 1996
- [c4]Florent de Dinechin, Sophie Robert:
Hierarchical Static Analysis Of Structured Systems Of Affine Recurrence Equations. ASAP 1996: 381- - [c3]Florent de Dinechin, Doran Wilde, Sanjay V. Rajopadhye, Rumen Andonov:
A Regular VLSI Array for an Irregular Algorithm. IRREGULAR 1996: 195-200 - 1995
- [c2]Helmut Weberpals, Florent Dupont de Dinechin:
A Localized Parallel Sorting Algorithm and its Implementation. PARCO 1995: 101-108 - 1993
- [c1]Helmut Weberpals, Florent Dupont de Dinechin:
Analysis of Parallel Algorithms for a Shared Virtual Memory Computer. PARCO 1993: 719-725
Coauthor Index
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last updated on 2024-08-05 20:21 CEST by the dblp team
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