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Rajeev Ranjan 0001
Person information
- affiliation: Jasper Design Automation, Mountain View, CA, USA
- affiliation (former): Synopsys Inc., Mountain View, CA, USA
- affiliation (former): University of California at Berkeley, CA, USA
Other persons with the same name
- Rajeev Ranjan — disambiguation page
- Rajeev Ranjan 0002
(aka: Rajeev K. Ranjan 0002, Rajeev Kumar Ranjan 0002) — Indian Institute of Technology, Department of Electronics Engineering, Dhanbad, India
- Rajeev Ranjan 0003
- Rajeev Ranjan 0004 — Hamburg University of Technology, Institute of Nano- and Medical Electronics, Germany
- Rajeev Ranjan 0005
- Rajeev Ranjan 0006
- Rajeev Ranjan 0007
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2000 – 2009
- 2009
- [c13]Rajeev K. Ranjan, Claudionor Coelho, Sebastian Skalberg:
Beyond verification: leveraging formal for debugging. DAC 2009: 648-651 - 2002
- [c12]David L. Dill, Nate James, Shishpal Rawat, Gérard Berry, Limor Fix, Harry Foster, Rajeev K. Ranjan, Gunnar Stålmarck, Curt Widdoes:
Formal verification methods: getting around the brick wall. DAC 2002: 576-577
1990 – 1999
- 1999
- [c11]Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton:
Using Combinational Verification for Sequential Circuits. DATE 1999: 138-144 - 1998
- [c10]Thomas R. Shiple, James H. Kukula, Rajeev K. Ranjan:
A Comparison of Presburger Engines for EFSM Reachability. CAV 1998: 280-292 - [c9]Bwolen Yang, Randal E. Bryant, David R. O'Hallaron, Armin Biere, Olivier Coudert, Geert Janssen, Rajeev K. Ranjan, Fabio Somenzi:
A Performance Study of BDD-Based Model Checking. FMCAD 1998: 255-289 - [c8]Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton:
On the optimization power of retiming and resynthesis transformations. ICCAD 1998: 402-407 - 1997
- [c7]Rajeev K. Ranjan, Wilsin Gosti, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions. ICCD 1997: 344-351 - [c6]Amit Mehrotra, Shaz Qadeer, Rajeev K. Ranjan, Randy H. Katz:
Benchmarking and Analysis of Architectures for CAD Applications. ICCD 1997: 670-675 - 1996
- [c5]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards
VIS: A System for Verification and Synthesis. CAV 1996: 428-432 - [c4]Jagesh V. Sanghavi, Rajeev K. Ranjan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
High Performance BDD Package By Exploiting Memory Hiercharchy. DAC 1996: 635-640 - [c3]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards
VIS. FMCAD 1996: 248-256 - [c2]Rajeev K. Ranjan, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Binary decision diagrams on network of workstation. ICCD 1996: 358-364 - 1994
- [c1]Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
HSIS: A BDD-Based Environment for Formal Verification. DAC 1994: 454-459
Coauthor Index
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