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Kazuaki J. Murakami
村上和彰
Person information
- unicode name: 村上和彰
- affiliation: Team Aibod, Fukuoka, Japan
- affiliation: Kyushu University, Graduate School of Information Science and Electrical Engineering, Fukuoka, Japan
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2010 – 2019
- 2019
- [j35]Israel Mendonça, Antoine Trouvé, Akira Fukuda, Kazuaki J. Murakami:
On Clustering Algorithms: Applications in Word-Embedding Documents. J. Comput. 14(2): 88-92 (2019) - 2018
- [j34]Hua Chen, Antoine Trouvé, Kazuaki J. Murakami, Akira Fukuda:
Semantic image retrieval for complex queries using a knowledge parser. Multim. Tools Appl. 77(9): 10733-10751 (2018) - [c69]Israel Mendonça
, Antoine Trouvé, Akira Fukuda, Kazuaki J. Murakami:
Exploring a Topical Representation of Documents for Recommendation Systems. iCAST 2018: 73-78 - 2017
- [j33]Hua Chen, Antoine Trouvé, Kazuaki J. Murakami, Akira Fukuda:
An intelligent annotation-based image retrieval system based on RDF descriptions. Comput. Electr. Eng. 58: 537-550 (2017) - 2016
- [j32]Antoine Trouvé, Arnaldo J. Cruz, Kazuaki J. Murakami, Masaki Arai, Tadashi Nakahira, Eiji Yamanaka:
Guide Automatic Vectorization by means of Machine Learning: A Case Study of Tensor Contraction Kernels. IEICE Trans. Inf. Syst. 99-D(6): 1585-1594 (2016) - 2015
- [j31]Krishna Chaitanya Nunna, Farhad Mehdipour, Antoine Trouvé, Kazuaki J. Murakami:
A survey on big data processing infrastructure: evolving role of FPGA. Int. J. Big Data Intell. 2(3): 145-156 (2015) - [j30]Hiromichi Abe, Takuya Kamizono, Kazuya Kinoshita, Kensuke Baba, Shigeru Takano, Kazuaki J. Murakami:
Towards Activity Recognition of Learners in On-line Lecture. J. Mobile Multimedia 11(3&4): 205-212 (2015) - [c68]Hadrien A. Clarke, Kazuaki J. Murakami:
MAD7F: A FPGA-based CMP Memory Architecture Simulation Framework. CANDAR 2015: 350-356 - [c67]Hiromichi Abe, Kazuya Kinoshita, Kensuke Baba
Analyzing Brain Waves for Activity Recognition of Learners. ICT-EurAsia/CONFENIS 2015: 64-73 - [c66]Antoine Trouvé, Kazuaki J. Murakami:
Interactive Visualization of Quantitative Data with G2D3. VINCI 2015: 154-155 - 2014
- [j29]Hiroshi Kataoka, Hiroaki Honda, Farhad Mehdipour, Nobuyuki Yoshikawa
A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits. IEICE Trans. Electron. 97-C(3): 141-148 (2014) - [j28]Antoine Trouvé, Arnaldo J. Cruz, Dhouha Ben Brahim, Hiroki Fukuyama, Kazuaki J. Murakami, Hadrien A. Clarke, Masaki Arai, Tadashi Nakahira, Eiji Yamanaka:
Predicting Vectorization Profitability Using Binary Classification. IEICE Trans. Inf. Syst. 97-D(12): 3124-3132 (2014) - [c65]Takuya Kamizono, Hiromichi Abe, Kensuke Baba, Shigeru Takano, Kazuaki J. Murakami:
Towards Activity Recognition of Learners by Kinect. IIAI-AAI 2014: 177-180 - [c64]Satoshi Kuboi, Kensuke Baba, Shigeru Takano, Kazuaki J. Murakami:
An Evaluation of a Complex Event Processing Engine. IIAI-AAI 2014: 190-193 - [c63]Mostafa Said, Farhad Mehdipour, Kazuaki J. Murakami, Mohamed El-Sayed:
A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias. MES@ISCA 2014: 9-16 - [c62]Hiromichi Abe, Kensuke Baba
Towards activity recognition of learners by simple electroencephalographs. ISDOC 2014: 161-164 - [c61]Hadrien A. Clarke, Antoine Trouvé, Kazuaki J. Murakami:
Accelerated design space pruning for CMP memory architectures: work-in-progress. SpringSim (HPS) 2014: 25 - 2013
- [c60]Krishna Chaitanya Nunna, Farhad Mehdipour, Kazuaki J. Murakami:
Early stage power management for 3D FPGAs considering hierarchical routing resources. ACM Great Lakes Symposium on VLSI 2013: 31-36 - [c59]Farhad Mehdipour, Krishna Chaitanya Nunna, Kazuaki J. Murakami:
A Smart Cyber-physical Systems-Based Solution for Pest Control (Work in Progress). GreenCom/iThings/CPScom 2013: 1248-1253 - [c58]Antoine Trouvé, Arnaldo J. Cruz, Hiroki Fukuyama, Jun Maki, Hadrien A. Clarke, Kazuaki J. Murakami, Masaki Arai, Tadashi Nakahira, Eiji Yamanaka:
Using Machine Learning in Order to Improve Automatic SIMD Instruction Generation. ICCS 2013: 1292-1301 - [c57]Hadrien A. Clarke, Antoine Trouvé, Kazuaki J. Murakami:
MAD7: a memory architecture simulator targeted at design space exploration. ICS 2013: 465-466 - 2012
- [j27]Antoine Trouvé, Kazuaki J. Murakami:
Optimisations Techniques for the Automatic ISA Customisation Algorithm. IEICE Trans. Inf. Syst. 95-D(2): 437-440 (2012) - [j26]Julien Tribino, Antoine Trouvé, Hadrien A. Clarke, Kazuaki J. Murakami:
PASTIS: a photonic arbitration with scalable token injection scheme. SIGARCH Comput. Archit. News 40(5): 76-81 (2012) - [j25]Hamid Noori
Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization. J. Supercomput. 60(2): 196-222 (2012) - [c56]Farhad Mehdipour, Krishna Chaitanya Nunna, Koji Inoue, Kazuaki J. Murakami:
A Three-Dimensional Integrated Accelerator. DSD 2012: 148-151 - [c55]Krishna Chaitanya Nunna, Farhad Mehdipour, Kazuaki J. Murakami:
Thermal-aware partitioning for 3D FPGAs. FPL 2012: 475-476 - [c54]Jonathan Antusiak, Antoine Trouvé, Kazuaki J. Murakami:
A Comparison of DAG and Mesh Topologies for Coarse-Grain Reconfigurable Array. IPDPS Workshops 2012: 227-233 - [c53]Yuki Abe, Hiroshi Sasaki, Martin Peres, Koji Inoue, Kazuaki J. Murakami, Shinpei Kato:
Power and Performance Analysis of GPU-Accelerated Systems. HotPower 2012 - [c52]Krishna Chaitanya Nunna, Farhad Mehdipour, Masayoshi Yoshimura, Kazuaki J. Murakami:
Methodology for early estimation of hierarchical routing resources in 3D FPGAs. VLSI-SoC 2012: 213-218 - 2011
- [j24]Hideki Miwa, Ryutaro Susukita, Hidetomo Shibamura, Tomoya Hirao, Jun Maki, Makoto Yoshida, Takayuki Kando, Yuichiro Ajima, Ikuo Miyoshi, Toshiyuki Shimizu, Yuji Oinaga, Hisashige Ando, Yuichi Inadomi, Koji Inoue, Mutsumi Aoyagi, Kazuaki J. Murakami:
NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers. IEICE Trans. Inf. Syst. 94-D(12): 2298-2308 (2011) - [j23]Farhad Mehdipour, Hiroaki Honda, Koji Inoue, Hiroshi Kataoka, Kazuaki J. Murakami:
A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuits. J. Syst. Archit. 57(1): 169-179 (2011) - [j22]Antoine Trouvé, Kazuaki J. Murakami:
Augmenting DR-ASIP flexibility through multi-mode custom instructions. SIGARCH Comput. Archit. News 39(4): 90-93 (2011) - [c51]Takaaki Hanada, Hiroshi Sasaki, Koji Inoue, Kazuaki J. Murakami:
Performance evaluation of 3D stacked multi-core processors with temperature consideration. 3DIC 2011: 1-5 - [c50]Farhad Mehdipour, Krishna Chaitanya Nunna, Lovic Gauthier, Koji Inoue, Kazuaki J. Murakami:
A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack. 3DIC 2011: 1-4 - [c49]Farhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, Koji Inoue, Kazuaki J. Murakami:
Routing architecture and algorithms for a superconductivity circuits-based computing hardware. CCECE 2011: 977-980 - [c48]Hadrien A. Clarke, Kazuaki J. Murakami:
Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits. DSD 2011: 503-508 - [c47]Amil A. Ilham
Evaluation and optimization of Java object ordering schemes. ICEEI 2011: 1-6 - 2010
- [c46]Farhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, Koji Inoue, Irina Kataeva, Kazuaki J. Murakami, Hiroyuki Akaike, Akira Fujimaki:
Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits. DATE 2010: 993-996
2000 – 2009
- 2009
- [j21]Takatsugu Ono, Koji Inoue, Kazuaki J. Murakami, Kenji Yoshida:
Reducing On-Chip DRAM Energy via Data Transfer Size Optimization. IEICE Trans. Electron. 92-C(4): 433-443 (2009) - [j20]Pradeep Rao, Kazuaki J. Murakami:
Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode. IEICE Trans. Electron. 92-C(10): 1265-1275 (2009) - [j19]Farhad Mehdipour, Hamid Noori
Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3182-3192 (2009) - [c45]Pradeep Rao, Kazuaki J. Murakami:
Empirical Performance Models for Java Workloads. ARCS 2009: 219-232 - [c44]Farhad Mehdipour, Hamid Noori
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. ASP-DAC 2009: 564-569 - [c43]Hyacinthe Nzigou Mamadou, Feng Long Gu, Vivien Oddou, Takeshi Nanri, Kazuaki J. Murakami:
A Dynamic Solution for Efficient MPI Collective Communications. CSO (1) 2009: 3-7 - [c42]Naoto Fukumoto, Kenichi Imazato, Koji Inoue, Kazuaki J. Murakami:
Performance balancing: software-based on-chip memory management for effective CMP executions. MEDEA@PACT 2009: 28-34 - [c41]Antoine Trouvé, Lovic Gauthier, Takayuki Kando, Benoit Ryder, Sebastien Pouzols, Pradeep Rao, Norifumi Yoshimatsu, Kazuaki J. Murakami:
Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units. ReConFig 2009: 231-236 - 2008
- [j18]Farhad Mehdipour, Hamid Noori
A gravity-directed temporal partitioning approach. IEICE Electron. Express 5(10): 366-373 (2008) - [j17]Naofumi Takagi
Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits. IEICE Trans. Electron. 91-C(3): 350-355 (2008) - [j16]Makoto Sugihara, Tohru Ishihara
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. IEICE Trans. Electron. 91-C(4): 410-417 (2008) - [j15]Hamid Noori
Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems. IEICE Trans. Electron. 91-C(4): 418-431 (2008) - [j14]Hamid Noori
A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions. IEICE Trans. Electron. 91-C(4): 497-508 (2008) - [j13]Hyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki J. Murakami:
Performance Models for MPI Collective Communications with Network Contention. IEICE Trans. Commun. 91-B(4): 1015-1024 (2008) - [j12]Makoto Sugihara, Yusuke Matsunaga, Kazuaki J. Murakami:
Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3451-3460 (2008) - [j11]Hamid Noori
An architecture framework for an adaptive extensible processor. J. Supercomput. 45(3): 313-340 (2008) - [c40]Naoto Fukumoto, Tomonobu Mihara, Koji Inoue, Kazuaki J. Murakami:
Analyzing the impact of data prefetching on Chip MultiProcessors. ACSAC 2008 - [c39]Farhad Mehdipour, Hamid Noori
Design space exploration for a coarse grain accelerator. ASP-DAC 2008: 685-690 - [c38]Hamid Noori
Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension. ISLPED 2008: 241-246 - [c37]Hamid Noori
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection. ISVLSI 2008: 363-368 - [c36]Ryutaro Susukita, Hisashige Ando, Mutsumi Aoyagi, Hiroaki Honda, Yuichi Inadomi, Koji Inoue, Shigeru Ishizuki, Yasunori Kimura, Hidemi Komatsu, Motoyoshi Kurokawa
Performance prediction of large-scale parallell system and application using macro-level simulation. SC 2008: 20 - 2007
- [j10]Makoto Sugihara, Kenta Nakamura, Yusuke Matsunaga, Kazuaki J. Murakami:
Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. IEICE Trans. Electron. 90-C(5): 1012-1020 (2007) - [j9]Mariko Sakamoto, Akira Katsuno, Go Sugizaki, Toshio Yoshida, Aiichiro Inoue, Koji Inoue, Kazuaki J. Murakami:
A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips. IEICE Trans. Electron. 90-C(10): 1972-1982 (2007) - [j8]Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami:
Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. IEICE Trans. Electron. 90-C(10): 1983-1991 (2007) - [j7]Farhad Mehdipour, Hamid Noori
Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. IEICE Trans. Inf. Syst. 90-D(12): 1956-1966 (2007) - [c35]Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki J. Murakami:
The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems. ESA 2007: 169-176 - [c34]Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Maziar Goudarzi
Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. DATE 2007: 325-330 - [c33]Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami:
Task scheduling for reliable cache architectures of multiprocessor systems. DATE 2007: 1490-1495 - [c32]Hamid Noori
The effect of temperature on cache size tuning for low energy embedded systems. ACM Great Lakes Symposium on VLSI 2007: 453-456 - [c31]Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami:
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. ICESS 2007: 249-260 - [c30]Takesi Soga, Kouji Kurihara, Takeshi Nanri, Motoyoshi Kurokawa
Dynamic Optimization of Load Balance in MPI Broadcast. PVM/MPI 2007: 387-388 - [c29]Hyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki J. Murakami, Guilherme de Melo Baptista Domingues:
Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication Algorithms. SBAC-PAD 2007: 203-210 - 2006
- [j6]Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Trans. Electron. 89-C(3): 377-383 (2006) - [c28]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Mehdi Sedighi, Koji Inoue:
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. Asia-Pacific Computer Systems Architecture Conference 2006: 219-230 - [c27]Koji Hashimoto, Vasily G. Moshnyaga, Kazuaki J. Murakami:
Circuit Area-latency Optimization Technique for High-precision Elementary Functions. APCCAS 2006: 1406-1409 - [c26]Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki J. Murakami, Hamid Noori:
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. ERSA 2006: 227-230 - [c25]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Koji Inoue, Mehdi Sedighi:
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. EUC 2006: 722-731 - [c24]Hamid Noori
A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. FPL 2006: 1-4 - [c23]Hyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki J. Murakami:
Collective Communication Costs Analysis over Gigabit Ethernet and InfiniBand. HiPC 2006: 547-559 - [c22]Farhad Mehdipour, Morteza Saheb Zamani
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. IPDPS 2006 - [c21]Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
A character size optimization technique for throughput enhancement of character projection lithography. ISCAS 2006 - [c20]Hamid Noori, Kazuaki J. Murakami:
Preliminary performance evaluation of an adaptive dynamic extensible processor for embedded applications. SAC 2006: 937-938 - [c19]Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki J. Murakami:
REDEFIS: a system with a redefinable instruction set processor. SBCCI 2006: 14-19 - 2005
- [j5]Reiko Komiya, Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami:
Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 862-868 (2005) - [c18]Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. SoC 2005: 137-140 - 2004
- [c17]Koji Inoue, Hidekazu Tanaka, Vasily G. Moshnyaga, Kazuaki J. Murakami:
A low-power I-cache design with tag-comparison reuse. SoC 2004: 61-67 - [c16]Makoto Sugihara, Kazuaki J. Murakami, Yusuke Matsunaga:
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. ISVLSI 2004: 179-186 - 2003
- [j4]Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami:
Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(4): 799-805 (2003) - 2002
- [c15]Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami:
Reducing power consumption of instruction ROMs by exploiting instruction frequency. APCCAS (2) 2002: 1-6 - [c14]Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami:
A Low Energy Set-Associative I-Cache with Extended BTB. ICCD 2002: 187- - [c13]Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami:
A history-based I-cache for low-energy multimedia applications. ISLPED 2002: 148-153 - [c12]Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami:
Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints. PACS 2002: 18-32 - 2001
- [c11]Takanori Okuma, Koji Hashimoto, Kazuaki J. Murakami:
Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication. ASP-DAC 2001: 37-38 - 2000
- [c10]Koji Inoue, Koji Kai, Kazuaki J. Murakami:
Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. Intelligent Memory Systems 2000: 169-178
1990 – 1999
- 1999
- [c9]Koji Inoue, Koji Kai, Kazuaki J. Murakami:
Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. HPCA 1999: 218-222 - [c8]Koji Inoue, Tohru Ishihara, Kazuaki J. Murakami:
Way-predicting set-associative cache for high performance and low energy consumption. ISLPED 1999: 273-275 - [c7]Koji Hashimoto, Hiroto Tomita, Koji Inoue, Katsuhiko Metsugi, Kazuaki J. Murakami, Shinjiro Inabata, So Yamada, Nobuaki Miyakawa, Hajime Takashima, Kunihiro Kitamura, Shigeru Obara, Takashi Amisaki, Kazutoshi Tanabe, Umpei Nagashima:
MOE: A Special-Purpose Parallel Computer for High-Speed, Large-Scale Molecular Orbital Calculation. SC 1999: 58 - 1998
- [c6]Taku Ohsawa, Koji Kai, Kazuaki J. Murakami:
Optimizing the DRAM refresh count for merged DRAM/logic LSIs. ISLPED 1998: 82-87 - 1993
- [c5]Takashi Hashimoto, Kazuaki J. Murakami, Tetsuo Hironaka, Hiroto Yasuura
A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. International Conference on Supercomputing 1993: 308-317 - 1992
- [c4]Tetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki J. Murakami, Shinji Tomita:
Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. ICS 1992: 272-281 - 1991
- [j3]Akira Fukuda, Kazuaki J. Murakami, Shinji Tomita:
Toward advanced parallel processing: exploiting parallelism at task and instruction levels. IEEE Micro 11(4): 16-19 (1991) - [j2]Morihiro Kuga, Kazuaki J. Murakami, Shinji Tomita:
DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture. SIGARCH Comput. Archit. News 19(4): 14-29 (1991)
1980 – 1989
- 1989
- [c3]Kazuaki J. Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita:
The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures. ICS 1989: 351-360 - [c2]Kazuaki J. Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita:
The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture. IFIP Congress 1989: 995-1000 - [c1]Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita:
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. ISCA 1989: 78-85 - 1988
- [j1]Kazuaki J. Murakami, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita:
An overview of the Kyushu University reconfigurable parallel processor. SIGARCH Comput. Archit. News 16(4): 130-137 (1988)
Coauthor Index
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