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Chu Yu
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2020 – today
- 2024
- [c24]Chu Yu, Yi-Ching Hung:
Generic Hardware Integrating Multiple Activation Functions for Deep Learning Applications. ICCE-Taiwan 2024: 333-334 - 2023
- [c23]Chu Yu, Po-Hao Hung, Jing-Huan Hong, Han-Yu Chiang:
Efficient Max Pooling Architecture with Zero-Padding for Convolutional Neural Networks. GCCE 2023: 747-748 - 2022
- [j16]Chu Yu
, Li-Zhong Hou:
Realization of a Real-Time Image Denoising System for Dashboard Camera Applications. IEEE Trans. Consumer Electron. 68(2): 181-190 (2022) - 2020
- [c22]Heri Prasetyo, Chih-Hsien Hsia
Friendly Appearance of Multiple Secret Sharing. ICCE-TW 2020: 1-2
2010 – 2019
- 2019
- [c21]Chu Yu, Mao-Wen Chen, Jin-Yu Chen, Jia-Hong Tang:
Peer Group and Hybrid Vector Filter for Removal of Impulse Noise in Color Images. ICCE-TW 2019: 1-2 - 2018
- [c20]Chu Yu, Kuang-Hsiao Lee, Jin-Yu Chen, Mao-Wen Chen, Yi-An Chen:
Three-Parallel Reed-Solomon Decoder using a Simplified Step-by-Step Algorithm. GCCE 2018: 105-106 - 2017
- [c19]Chu Yu, Zhi-Hong Lin, Ting-Wei Hsu, Mao-Wen Chen, Yi-An Chen:
Lower bit-error-rate polar-LDPC concatenated coding for wireless communication systems. GCCE 2017: 1-2 - [c18]Chu Yu, Kuang-Hsiao Lee, Chien-Feng Kuo:
Low-complexity twiddle factor generator for FFT processors. ICCE 2017: 350-351 - 2015
- [j15]Mao-Hsu Yen, Hung-Kuan Yen
Comment on "On Optimal Hyperuniversal and Rearrangeable Switch Box Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(7): 1133-1137 (2015) - [j14]Chu Yu, Yu-Shan Su:
Two-Mode Reed-Solomon Decoder Using A Simplified Step-by-Step Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 62-II(11): 1093-1097 (2015) - [j13]Chu Yu, Mao-Hsu Yen:
Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile WiMAX Systems. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1793-1800 (2015) - [c17]Li-Zhon Hou, Chien-Feng Kuo, Zhi-Hong Lin, Chu Yu:
Efficient image denoising scheme for removal of impulse noise. GCCE 2015: 298-299 - [c16]Bor-Shing Lin, Wei-Ren Chou, Chu Yu, Po-Hsun Cheng, Po-Jui Tseng, Sao-Jie Chen
An effective spatial-temporal denoising approach for depth images. DSP 2015: 647-651 - [c15]Jung-Hong Po, Sao-Jie Chen
Variable code length soft-output decoder of polar codes. DSP 2015: 655-658 - 2014
- [j12]Hwai-Tsu Hu, Hsien-Hsin Chou
Incorporation of perceptually adaptive QIM with singular value decomposition for blind audio watermarking. EURASIP J. Adv. Signal Process. 2014: 12 (2014) - [c14]Chu Yu, Ho-Sheng Chuang, Bor-Shing Lin, Po-Hsun Cheng, Sao-Jie Chen
Improvement on a block-serial fully-overlapped QC-LDPC decoder for IEEE 802.11n. ICCE 2014: 446-447 - 2013
- [j11]Mao-Hsu Yen
A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design. VLSI Design 2013: 103473:1-103473:15 (2013) - [c13]Mao-Hsu Yen, Chu Yu, Yih-Hsia Lin, Chang-Hsien Chung:
Hyper-Universal Switch Network for FPIC Design. CISIS 2013: 456-460 - [c12]Chu Yu:
A 128/512/1024/2048-point pipeline FFT/IFFT architecture for mobile WiMAX. GCCE 2013: 243-244 - [c11]Chu Yu, Yu-Shan Su, Bor-Shing Lin, Po-Hsun Cheng, Sao-Jie Chen
A dual-code-rate memoryless Viterbi decoder for wireless communication systems. ICCE 2013: 578-579 - [c10]Yu-Shan Su, Chu Yu, Bor-Shing Lin, Po-Hsun Cheng, Sao-Jie Chen
Design of a (255, 239) Reed-Solomon decoder using a simplified step-by-step algorithm. ISCE 2013: 247-248 - 2012
- [j10]Hwai-Tsu Hu, Chu Yu:
A Perceptually Adaptive QIM Scheme for Efficient Watermark Synchronization. IEICE Trans. Inf. Syst. 95-D(12): 3097-3100 (2012) - [j9]Hwai-Tsu Hu, Chu Yu:
A HMM-WDLT framework for HNM-based voice conversion with parametric adjustment in formant bandwidth, duration and excitation. Int. J. Speech Technol. 15(2): 215-225 (2012) - [j8]Chu Yu, Chen-Hen Sung, Chien-Hung Kuo, Mao-Hsu Yen, Sao-Jie Chen
Design and implementation of a low-power OFDM receiver for wireless communications. IEEE Trans. Consumer Electron. 58(3): 739-745 (2012) - [c9]Po-Hsun Cheng, Shun-Hsiang Hu, Yu-Pao Lin, Hsiao-Chi Hsieh, Bor-Shing Lin, Chu Yu, Sao-Jie Chen
A Ubiquitous Scheme for a One-to-Many Switching Tunnel for Healthcare Utilization. CICSyN 2012: 389-392 - [c8]Chu Yu, Chien-Hung Kuo, Chen-Hen Sung, Mao-Hsu Yen, Sao-Jie Chen
Design of a low-power OFDM baseband receiver for wireless communications. ICCE 2012: 548-549 - 2011
- [j7]Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen
A low-power 64-point pipeline FFT/IFFT processor for OFDM applications. IEEE Trans. Consumer Electron. 57(1): 40 (2011) - 2010
- [j6]Meng-Hsueh Chiang, Yi-Bo Liao, Jun-Tin Lin, Wei-Chou Hsu, Chu Yu, Pei-Chia Chiang, Y.-Y. Hsu, W.-H. Liu, Shyh-Shyuan Sheu, Keng-Li Su, Ming-Jer Kao, Ming-Jinn Tsai:
Low power design of phase-change memory based on a comprehensive model. IET Comput. Digit. Tech. 4(4): 285-292 (2010) - [c7]Jui-Chieh Lin, Minja Hsieh, Ming-Jung Fan-Chiang, Song-Yen Mao, Chu Yu, Sao-Jie Chen
Perfect shuffling for cycle efficient puncturer and interleaver for software defined radio. ISCAS 2010: 3965-3968 - [c6]Sao-Jie Chen
ARAL-CR: An adaptive reasoning and learning cognitive radio platform. ICSAMOS 2010: 324-331
2000 – 2009
- 2009
- [j5]Hwai-Tsu Hu, Chu Yu:
Combining HMM and Weighted Deviation Linear Transformation for Highband Speech Parameter Estimation. IEICE Trans. Inf. Syst. 92-D(7): 1488-1490 (2009) - [c5]Jia-Wei Lin, Da-Tong Yen, Wei-Yi Hu, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen
A 900 MHz to 5.2 GHz Dual-loop Feedback Multi-band LNA. ISCAS 2009: 1024-1027 - [c4]Jui-Chieh Lin, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen
Parallel implementation of convolution encoder for software defined radio on DSP architecture. ICSAMOS 2009: 180-186 - [c3]Jui-Chieh Lin, Minja Hsieh, Ming-Jung Fan-Chiang, Chu Yu, Sao-Jie Chen
An instruction set architecture independent design method for embedded OFDM-based software defined transmitter. SoCC 2009: 207-210 - 2007
- [c2]Chu Yu, Hwai-Tsu Hu:
A compact pipelined architecture with high-throughput for context-based binary arithmetic coding. SoCC 2007: 33-36 - 2003
- [j4]Hwai-Tsu Hu, Shun-Ta Hsu, Chu Yu:
Determination of glottal closure instants by harmonic superposition. Signal Process. 83(9): 1985-1995 (2003) - [j3]Chu Yu:
An efficient architecture for 2-D biorthogonal inverse discrete wavelet transforms. IEEE Trans. Consumer Electron. 49(2): 427-432 (2003) - [j2]Chu Yu, Hwai-Tsu Hu, Chen-Yen Lin:
Design and implantation of an ASIC architecture for 1.6 kbps speech synthesis. IEEE Trans. Consumer Electron. 49(3): 731-736 (2003)
1990 – 1999
- 1999
- [j1]Chu Yu, Sao-Jie Chen
Design of an efficient VLSI architecture for 2-D discrete wavelet transforms. IEEE Trans. Consumer Electron. 45(1): 135-140 (1999) - [c1]Chu Yu, Sao-Jie Chen:
Efficient VLSI architecture for 2-D inverse discrete wavelet transforms. ISCAS (3) 1999: 524-527
Coauthor Index
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