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Geoffrey W. Burr
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2020 – today
- 2023
- [j16]Stefano Ambrogio, Pritish Narayanan, Atsuya Okazaki
, Andrea Fasoli, Charles Mackin
An analog-AI chip for energy-efficient speech recognition and transcription. Nat. 620(7975): 768-775 (2023) - [j15]Shubham Jain
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh. IEEE Trans. Very Large Scale Integr. Syst. 31(1): 114-127 (2023) - [c17]Martin M. Frank, Ning Li, Malte J. Rasch, Shubham Jain, Ching-Tzu Chen, Ramachandran Muralidhar, Jin-Ping Han, Vijay Narayanan
Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited). IRPS 2023: 1-10 - [c16]Hsinyu Tsai, Pritish Narayanan, Shubham Jain, Stefano Ambrogio, Kohji Hosokawa
Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited). ISCAS 2023: 1-5 - [c15]Geoffrey W. Burr, Pritish Narayanan, Stefano Ambrogio, Atsuya Okazaki, Hsinyu Tsai, Kohji Hosokawa
Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited). VLSI Technology and Circuits 2023: 1-2 - [i1]Malte J. Rasch, Charles Mackin, Manuel Le Gallo, An Chen, Andrea Fasoli, Frédéric Odermatt, Ning Li, S. R. Nandakumar, Pritish Narayanan, Hsinyu Tsai, Geoffrey W. Burr, Abu Sebastian, Vijay Narayanan
Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators. CoRR abs/2302.08469 (2023) - 2022
- [j14]Geoffrey W. Burr
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips. IEEE Des. Test 39(3): 18-27 (2022) - [c14]Atsuya Okazaki
Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers. ISCAS 2022: 3319-3323 - 2021
- [j13]Katie Spoon, Hsinyu Tsai, An Chen, Malte J. Rasch, Stefano Ambrogio, Charles Mackin
Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices. Frontiers Comput. Neurosci. 15: 675741 (2021) - [c13]Robert L. Bruce, Syed Ghazi Sarwat
Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation. IRPS 2021: 1-6 - [c12]Kohji Hosokawa
Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited). ISCAS 2021: 1-5 - 2020
- [c11]Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Charles Mackin
Accelerating Deep Neural Networks with Analog Memory Devices. AICAS 2020: 149-152 - [c10]Charles Mackin
Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges. IRPS 2020: 1-10 - [c9]Andrea Fasoli, Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Charles Mackin, Katherine Spoon, Alexander M. Friz, An Chen, Geoffrey W. Burr:
Optimization of Analog Accelerators for Deep Neural Networks Inference. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j12]Massimo Giordano, Giorgio Cristiano, Koji Ishibashi, Stefano Ambrogio, Hsinyu Tsai, Geoffrey W. Burr
Analog-to-Digital Conversion With Reconfigurable Function Mapping for Neural Networks Activation Function Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 367-376 (2019) - [j11]Hung-Yang Chang, Pritish Narayanan
AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed. IBM J. Res. Dev. 63(6): 8:1-8:14 (2019) - [j10]Geoffrey W. Burr:
A role for analogue memory in AI hardware. Nat. Mach. Intell. 1(1): 10-11 (2019) - [c8]Eduard A. Cartier, Wanki Kim, Nanbo Gong, Tayfun Gokmen, Martin M. Frank, Douglas M. Bishop, Youngseok Kim, Seyoung Kim
Reliability Challenges with Materials for Analog Computing. IRPS 2019: 1-10 - [c7]Alessandro Fumarola, Yusuf Leblebici, Pritish Narayanan, Robert M. Shelby, L. L. Sanchez, Geoffrey W. Burr, Kibong Moon, J. Jang, Hyunsang Hwang, Severin Sidler:
Non-filamentary non-volatile memory elements as synapses in neuromorphic systems. NVMTS 2019: 1-6 - 2018
- [j9]Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Robert M. Shelby, Irem Boybat, Carmelo di Nolfo, Severin Sidler, Massimo Giordano, Martina Bodini, Nathan C. P. Farinha, Benjamin Killeen
Equivalent-accuracy accelerated neural-network training using analogue memory. Nat. 558(7708): 60-67 (2018) - 2017
- [j8]Pritish Narayanan, Alessandro Fumarola, Lucas L. Sanches
Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory. IBM J. Res. Dev. 61(4-5): 11:1-11:11 (2017) - [c6]Irem Boybat
Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique. ICRC 2017: 1-8 - [c5]Geoffrey W. Burr, Pritish Narayanan, Robert M. Shelby, Stefano Ambrogio, Hsinyu Tsai, Scott L. Lewis, Kohji Hosokawa
Neuromorphic devices and architectures for next-generation cognitive computing. ISCAS 2017: 1-4 - [c4]Pritish Narayanan, Lucas L. Sanches
Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays. ISCAS 2017: 1-4 - 2016
- [j7]Geoffrey W. Burr, Matthew J. BrightSky, Abu Sebastian
Recent Progress in Phase-Change Memory Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 146-162 (2016) - [j6]Pritish Narayanan, Geoffrey W. Burr, Kumar Virwani, Bülent N. Kurdi:
Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 330-338 (2016) - [c3]Severin Sidler
Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response. ESSDERC 2016: 440-443 - [c2]Alessandro Fumarola, Pritish Narayanan, Lucas L. Sanches, Severin Sidler
Accelerating machine learning with Non-Volatile Memory: Exploring device and circuit tradeoffs. ICRC 2016: 1-8 - 2015
- [c1]Robert M. Shelby, Geoffrey W. Burr, Irem Boybat
Non-volatile memory as hardware synapse in neuromorphic computing: A first look at reliability issues. IRPS 2015: 6 - 2013
- [j5]Bryan L. Jackson, Bipin Rajendran
Nanoscale electronic synapses using phase change devices. ACM J. Emerg. Technol. Comput. Syst. 9(2): 12:1-12:20 (2013)
2000 – 2009
- 2008
- [j4]Geoffrey W. Burr, Bülent N. Kurdi, J. Campbell Scott, Chung Hon Lam, Kailash Gopalakrishnan, Rohit S. Shenoy:
Overview of candidate device technologies for storage-class memory. IBM J. Res. Dev. 52(4-5): 449-464 (2008) - [j3]Simone Raoux, Geoffrey W. Burr, Matthew J. Breitwisch, Charles T. Rettner, Yi-Chou Chen, Robert M. Shelby, Martin Salinga, Daniel Krebs, Shih-Hung Chen, Hsiang-Lan Lung, Chung Hon Lam:
Phase-change random access memory: A scalable technology. IBM J. Res. Dev. 52(4-5): 465-480 (2008) - 2000
- [j2]Jonathan J. Ashley, Maria-Pilar Bernal, Geoffrey W. Burr, Hans Coufal, Harald Guenther, John A. Hoffnagle, C. Michael Jefferson, Brian H. Marcus, Roger M. Macfarlane, Robert M. Shelby, Glenn T. Sincerbox:
Holographic data storage technology. IBM J. Res. Dev. 44(3): 341-368 (2000)
1990 – 1999
- 1998
- [j1]Demetri Psaltis, Geoffrey W. Burr:
Holographic Data Storage. Computer 31(2): 52-60 (1998)
Coauthor Index
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