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Amir Kaivani
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2010 – 2019
- 2016
- [j9]Amir Kaivani, Seok-Bum Ko
:
Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1208-1211 (2016) - 2014
- [j8]Liu Han, Amir Kaivani, Seok-Bum Ko
Area Efficient Sequential Decimal Fixed-point Multiplier. J. Signal Process. Syst. 75(1): 39-46 (2014) - [c5]Amir Kaivani, Seok-Bum Ko
High-speed FFT processors based on redundant number systems. ISCAS 2014: 2237-2240 - 2013
- [j7]Amir Kaivani, Seok-Bum Ko
Decimal SRT Square Root: Algorithm and Architecture. Circuits Syst. Signal Process. 32(5): 2137-2150 (2013) - [j6]Amir Kaivani, Seok-Bum Ko
Decimal Division Algorithms: The Issue of Partial Remainders. J. Signal Process. Syst. 73(2): 181-188 (2013) - [c4]Amir Kaivani, Seok-Bum Ko
Decimal signed digit addition using stored transfer encoding. CCECE 2013: 1-4 - 2012
- [c3]Amir Kaivani, Li Chen, Seok-Bum Ko
High-frequency sequential decimal multipliers. ISCAS 2012: 3045-3048 - 2011
- [j5]Amir Kaivani, Ghassem Jaberipur:
Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture. Comput. J. 54(11): 1798-1809 (2011) - [j4]Amir Kaivani, Adel Hosseiny, Ghassem Jaberipur:
Improving the speed of decimal division. IET Comput. Digit. Tech. 5(5): 393-404 (2011) - 2010
- [j3]Amir Kaivani, Ghassem Jaberipur:
Fully redundant decimal addition and subtraction using stored-unibit encoding. Integr. 43(1): 34-41 (2010)
2000 – 2009
- 2009
- [j2]Ghassem Jaberipur, Amir Kaivani:
Improving the Speed of Parallel Decimal Multiplication. IEEE Trans. Computers 58(11): 1539-1552 (2009) - 2007
- [j1]Ghassem Jaberipur, Amir Kaivani:
Binary-coded decimal digit multipliers. IET Comput. Digit. Tech. 1(4): 377-381 (2007) - [c2]Saeid Gorgin
Reversible Barrel Shifters. AICCSA 2007: 479-483 - 2006
- [c1]Amir Kaivani, Ali Zakerolhosseini, Saeid Gorgin
Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in IEEE-754R. ICIT 2006: 273-276
Coauthor Index
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