default search action
Anindya Sundar Dhar
A. S. Dhar 0001
Person information
- affiliation: Indian Institute of Technology Kharagpur, India
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [j54]Rajen Kumar Patra
, Anindya Sundar Dhar:
A Generalized Rearranged Coprime Array Configuration for Direction-of-Arrival Estimation with Increased Degrees of Freedom. Circuits Syst. Signal Process. 43(9): 6023-6034 (2024) - [c33]Ayan Palchaudhuri, Anindya Sundar Dhar:
FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation. VLSID 2024: 617-622 - 2023
- [j53]Rajen Kumar Patra
An Improved CACIS Configuration for DOA Estimation with Enhanced Degrees of Freedom. Circuits Syst. Signal Process. 42(3): 1860-1872 (2023) - [j52]Rajen Kumar Patra
A Novel Translated Coprime Array Configuration for Moving Platform in Direction-of-Arrival Estimation. Circuits Syst. Signal Process. 42(4): 2494-2505 (2023) - [j51]Rajen Kumar Patra
Optimal Coprime Array: Properties, Optimization, and k-times extension. Circuits Syst. Signal Process. 42(6): 3770-3794 (2023) - [j50]Rajen Kumar Patra
Unfolded Coprime Transformed Nested Arrays for Increased DOF and Negligible Mutual Coupling. Circuits Syst. Signal Process. 42(12): 7275-7296 (2023) - 2022
- [j49]Rajen Kumar Patra
A special coprime array configuration for increased degrees of freedom. Digit. Signal Process. 122: 103369 (2022) - [j48]Ayan Palchaudhuri
FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion. J. Parallel Distributed Comput. 167: 50-63 (2022) - [j47]Rajen Kumar Patra
Novel Moving Coprime Array Configurations for Real-Valued Sources. IEEE Signal Process. Lett. 29: 657-661 (2022) - [j46]Rajen Kumar Patra
A Novel $k$-times Extended Coprime Array for DOA Estimation With Increased Degrees of Freedom. IEEE Signal Process. Lett. 29: 1402-1406 (2022) - [j45]Avishek Sinha Roy
ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design. IEEE Trans. Emerg. Top. Comput. 10(4): 2072-2078 (2022) - 2021
- [j44]Ayan Banerjee
A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation. Circuits Syst. Signal Process. 40(1): 311-334 (2021) - [j43]Ayan Palchaudhuri
Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support. J. Parallel Distributed Comput. 151: 13-23 (2021) - [j42]Rajen Kumar Patra
A Novel Nested Array for Real-Valued Sources Exploiting Array Motion. IEEE Signal Process. Lett. 28: 1375-1379 (2021) - [j41]Ayan Palchaudhuri
Design Automation for Tree-based Nearest Neighborhood-aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion. ACM Trans. Design Autom. Electr. Syst. 26(4): 31:1-31:34 (2021) - 2020
- [j40]Ayan Palchaudhuri
Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables. J. Electron. Test. 36(4): 519-536 (2020) - [j39]Avishek Sinha Roy
SIBAM - Sign Inclusive Broken Array Multiplier Design for Error Tolerant Applications. IEEE Trans. Circuits Syst. 67-II(11): 2702-2706 (2020) - [j38]Avishek Sinha Roy
On Fast and Exact Computation of Error Metrics in Approximate LSB Adders. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 876-889 (2020) - [c32]Ayan Palchaudhuri
Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability. FCCM 2020: 207 - [c31]Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar:
Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion. FPGA 2020: 316
2010 – 2019
- 2019
- [j37]Ayan Palchaudhuri
Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations. J. Electron. Test. 35(6): 779-796 (2019) - [j36]Tanmai Kulshreshtha
Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm. IET Circuits Devices Syst. 13(2): 251-258 (2019) - [j35]Ayan Palchaudhuri
Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies. J. Parallel Distributed Comput. 130: 110-125 (2019) - [j34]Atin Mukherjee
Triple transistor based triple modular redundancy with embedded voter circuit. Microelectron. J. 87: 101-109 (2019) - [j33]Subrahmanyam Mula
Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1223-1227 (2019) - [j32]Kailash Chandra Ray
CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism. J. Signal Process. Syst. 91(5): 539-550 (2019) - [c30]Ayan Palchaudhuri
FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation. ACSSC 2019: 1555-1559 - [c29]Atin Mukherjee
Defect Tolerant Majority Voter Design Using Triple Transistor Redundancy. iSES 2019: 63-68 - [c28]Ayan Palchaudhuri
VLSI Architectures for Jacobi Symbol Computation. VLSID 2019: 335-340 - 2018
- [j31]Tanmai Kulshreshtha
CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation. Circuits Syst. Signal Process. 37(11): 5101-5126 (2018) - [j30]Atin Mukherjee
Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method. Circuits Syst. Signal Process. 37(12): 5595-5615 (2018) - [j29]Subrahmanyam Mula
Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1750-1762 (2018) - [j28]Kailash Chandra Ray
An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform. J. Signal Process. Syst. 90(11): 1569-1580 (2018) - [c27]Ayan Palchaudhuri
Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs. ARC 2018: 537-550 - [c26]Ayan Palchaudhuri
Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support. IPDPS Workshops 2018: 218-221 - [c25]Avishek Sinha Roy, Anindya Sundar Dhar:
A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders. ISCAS 2018: 1-5 - [c24]Ayan Palchaudhuri
High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization. VLSID 2018: 186-191 - [i2]Avishek Sinha Roy, Anindya Sundar Dhar:
A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders. CoRR abs/1803.08005 (2018) - 2017
- [j27]Ayan Palchaudhuri
Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations. J. Electron. Test. 33(4): 529-537 (2017) - [j26]Chandrakanth Mamidala, Anindya Sundar Dhar:
High-performance VLSI architectures for M-PSK modems. IET Circuits Devices Syst. 11(2): 166-172 (2017) - [j25]Amitava Ghosh
Fraction phase based low energy frequency calibration: analysis and design. IET Circuits Devices Syst. 11(3): 241-249 (2017) - [j24]Tanmai Kulshreshtha
CORDIC-based Hann windowed sliding DFT architecture for real-time spectrum analysis with bounded error-accumulation. IET Circuits Devices Syst. 11(5): 487-495 (2017) - [j23]Ayan Palchaudhuri, Amrit Anand Amresh, Anindya Sundar Dhar:
Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs. J. Cell. Autom. 12(3-4): 217-247 (2017) - [j22]Atin Mukherjee
Triple transistor based fault tolerance for resource constrained applications. Microelectron. J. 68: 1-6 (2017) - [j21]Subrahmanyam Mula
Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2588-2601 (2017) - [j20]Sumantra Sarkar
Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3057-3066 (2017) - [c23]Ayan Palchaudhuri
Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs. HiPC 2017: 104-113 - [c22]Mamata Panigrahy
Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder. VDAT 2017: 376-387 - [c21]Ayan Palchaudhuri
Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs. VDAT 2017: 594-606 - [i1]Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar:
Algorithm/Architecture Co-design of Proportionate-type LMS Adaptive Filters for Sparse System Identification. CoRR abs/1703.10658 (2017) - 2016
- [j19]Mamata Panigrahy
Low-Delay Parallel Architecture for Fractal Image Compression. Circuits Syst. Signal Process. 35(3): 897-917 (2016) - [j18]Rohan Mukherjee, Vikrant Mahajan, Anindya Sundar Dhar, Indrajit Chakrabarti:
High Performance VISI Design of Diamond Search Algorithm for Fast Motion Estimation. J. Circuits Syst. Comput. 25(9): 1650114:1-1650114:16 (2016) - [j17]Kausik Ghosh, Anindya Sundar Dhar:
A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation. J. Real Time Image Process. 11(1): 37-46 (2016) - [j16]Kausik Ghosh, Anindya Sundar Dhar:
Erratum to: A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation. J. Real Time Image Process. 11(1): 47 (2016) - [j15]Atin Mukherjee
Choice of granularity for reliable circuit design using dynamic reconfiguration. Microelectron. Reliab. 63: 291-303 (2016) - [c20]Ayan Palchaudhuri
High performance bit-sliced pipelined comparator tree for FPGAs. VDAT 2016: 1-6 - [c19]Avishek Sinha Roy, N. Prasad
Approximate conditional carry adder for error tolerant applications. VDAT 2016: 1-6 - [c18]Ayan Palchaudhuri
Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs. VLSID 2016: 433-438 - 2015
- [j14]Rohan Mukherjee, Keyur Sheth, Anindya Sundar Dhar, Indrajit Chakrabarti, Somnath Sengupta:
High Performance VLSI Architecture for Three-Step Search Algorithm. Circuits Syst. Signal Process. 34(5): 1595-1612 (2015) - [j13]Atin Mukherjee
Real-time fault-tolerance with hot-standby topology for conditional sum adder. Microelectron. Reliab. 55(3-4): 704-712 (2015) - [c17]Atin Mukherjee
New triple-transistor based defect-tolerant systems for reliable digital architectures. ISCAS 2015: 1917-1920 - 2014
- [j12]Kailash Chandra Ray, Anindya Sundar Dhar:
CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis. J. Signal Process. Syst. 74(2): 235-244 (2014) - [c16]Amitava Ghosh
An ultra low power MICS/ISM band transmitter in 0.18 μm CMOS. VDAT 2014: 1-6 - [c15]Mamata Panigrahy
VLSI design of fast fractal image encoder. VDAT 2014: 1-2 - 2013
- [j11]Boppana Lakshmi, A. S. Dhar:
VLSI architecture for parallel radix-4 CORDIC. Microprocess. Microsystems 37(1): 79-86 (2013) - [j10]Ayan Banerjee, Anindya Sundar Dhar:
Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer. J. Signal Process. Syst. 70(1): 39-48 (2013) - 2012
- [j9]Amitava Ghosh
A Variable RF Carrier Modulation Scheme for Ultralow Power Wireless Body-Area Network. IEEE Syst. J. 6(2): 305-316 (2012) - [c14]Atin Mukherjee
Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture. ISED 2012: 92-96 - [c13]Atin Mukherjee
Design of a Fault-Tolerant Conditional Sum Adder. VDAT 2012: 217-222 - [c12]Nilanjan Chattaraj
Random Access Analog Memory (RA2M) for Video Signal Application. VLSI Design 2012: 39-44 - 2011
- [j8]Boppana Lakshmi, A. S. Dhar:
VLSI architecture for low latency radix-4 CORDIC. Comput. Electr. Eng. 37(6): 1032-1042 (2011) - 2010
- [j7]Kaushik Bhattacharyya, Rakesh Biswas
Architectural design and FPGA implementation of radix-4 CORDIC processor. Microprocess. Microsystems 34(2-4): 96-101 (2010) - [j6]Boppana Lakshmi, A. S. Dhar:
CORDIC Architectures: A Survey. VLSI Design 2010: 794891:1-794891:19 (2010) - [c11]Ashis Kumar Mal, Om Prakash Hari, Rishi Todani, Anindya Sundar Dhar:
Design of DXT architecture using current switched integrator. APCCAS 2010: 576-579
2000 – 2009
- 2008
- [j5]Kailash Chandra Ray, A. S. Dhar:
High Throughput VLSI Architecture for Blackman Windowing in Real Time Spectral Analysis. J. Comput. 3(5): 54-59 (2008) - [c10]Boppana Lakshmi, A. S. Dhar:
Low Latency VLSI Architecture for the Radix-4 CORDIC Algorithm. ICIIS 2008: 1-5 - 2006
- [c9]C. Thakkar, Anindya Sundar Dhar:
Sampled analog architecture for 2-D DCT. ISCAS 2006 - 2005
- [j4]Ayan Banerjee, Anindya Sundar Dhar:
Novel architecture for QAM modulator-demodulator and its generalization to multicarrier modulation. Microprocess. Microsystems 29(7): 351-357 (2005) - [j3]Mrityunjoy Chakraborty, Anindya Sundar Dhar, Moon Ho Lee:
A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC. IEEE Trans. Circuits Syst. II Express Briefs 52-II(9): 530-534 (2005) - [c8]Arindam Basu
Design Issues in Switched Capacitor Ladder Filters. VLSI Design 2005: 862-865 - 2004
- [c7]Arindam Basu, Ashis Kumar Mal, Anindya Sundar Dhar:
Digital controlled analog architecture for DCT and DST using capacitor switching. ISCAS (2) 2004: 309-312 - [c6]Ashis Kumar Mal, Arindam Basu, Anindya Sundar Dhar:
Sampled analog architecture for DCT and DST. ISCAS (2) 2004: 825-828 - [c5]Ashis Kumar Mal, Anindya Sundar Dhar:
Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors. VLSI Design 2004: 666-669 - 2003
- [c4]Ashis Kumar Mal, Anindya Sundar Dhar:
Analog sampled data architecture for discrete Hartley transform for prime N. ICECS 2003: 152-155 - 2001
- [j2]Ayan Banerjee, Anindya Sundar Dhar, Swapna Banerjee:
FPGA realization of a CORDIC based FFT processor for biomedical signal processing. Microprocess. Microsystems 25(3): 131-142 (2001) - [j1]Koushik Maharatna
A VLSI array architecture for realization of DFT, DHT, DCT and DST. Signal Process. 81(9): 1813-1822 (2001) - [c3]Mrityunjoy Chakraborty, Anindya Sundar Dhar, Suraiya Pervin:
CORDIC realization of the transversal adaptive filter using a trigonometric LMS algorithm. ICASSP 2001: 1225-1228 - 2000
- [c2]Mrityunjoy Chakraborty, Suraiya Pervin, Anindya Sundar Dhar:
Systolizing the adaptive decision feedback equalizer using a symbolic state space formulation. EUSIPCO 2000: 1-4
1990 – 1999
- 1992
- [c1]Anindya Sundar Dhar:
An Array Architecture for Computing KLT Basis Vectors. VLSI Design 1992: 167-170
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-09-10 01:17 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: