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Debapriya Chatterjee
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2020 – today
- 2024
- [c14]Hasini Witharana, Debapriya Chatterjee, Prabhat Mishra:
Verifying Memory Confidentiality and Integrity of Intel TDX Trusted Execution Environments. HOST 2024: 44-54 - 2022
- [c13]José E. Moreira, Debapriya Chatterjee, Kattamuri Ekanadham, Arnold Flores:
Return-oriented programming protection in the IBM POWER10. CF 2022: 173-176
2010 – 2019
- 2018
- [j2]Klaus-Dieter Schubert, Syed Saif Abrar, Duane Averill, Ellen Bauman, Aaron C. Brown, Ron Cash, Debapriya Chatterjee, John Gullickson, Mark Nelson, Kevin A. Pasnik, Krishnan Sugavanam:
Addressing verification challenges of heterogeneous systems based on IBM POWER9. IBM J. Res. Dev. 62(4/5): 11:1-11:12 (2018) - 2014
- [c12]Chang-Hong Hsu, Debapriya Chatterjee, Ronny Morad, Raviv Gal, Valeria Bertacco:
ArChiVED: Architectural checking via event digests for high performance validation. DATE 2014: 1-6 - 2013
- [b1]Debapriya Chatterjee:
Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge. University of Michigan, USA, 2013 - [c11]Valeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, Anirudh M. Kaushik, Hiren D. Patel:
On the use of GP-GPUs for accelerating compute-intensive EDA applications. DATE 2013: 1357-1366 - [c10]Debapriya Chatterjee, Biruk Mammo, Doowon Lee, Raviv Gal, Ronny Morad, Amir Nahir, Avi Ziv, Valeria Bertacco:
Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms. ICCAD 2013: 311-317 - 2012
- [c9]Nicola Bombieri, Sara Vinco, Valeria Bertacco, Debapriya Chatterjee:
SystemC simulation on GP-GPUs: CUDA vs. OpenCL. CODES+ISSS 2012: 343-352 - [c8]Sara Vinco, Debapriya Chatterjee, Valeria Bertacco, Franco Fummi:
SAGA: SystemC acceleration on GPU architectures. DAC 2012: 115-120 - [c7]Debapriya Chatterjee, Anatoly Koyfman, Ronny Morad, Avi Ziv, Valeria Bertacco:
Checking architectural outputs instruction-by-instruction on acceleration platforms. DAC 2012: 955-961 - [c6]Biruk Mammo, Debapriya Chatterjee, Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad, Valeria Bertacco:
Approximating checkers for simulation acceleration. DATE 2012: 153-158 - 2011
- [j1]Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco:
Gate-Level Simulation with GPU Computing. ACM Trans. Design Autom. Electr. Syst. 16(3): 30:1-30:26 (2011) - [c5]Debapriya Chatterjee, Calvin McCarter, Valeria Bertacco:
Simulation-based signal selection for state restoration in silicon debug. ICCAD 2011: 595-601 - 2010
- [c4]Debapriya Chatterjee, Valeria Bertacco:
EQUIPE: Parallel equivalence checking with GP-GPUs. ICCD 2010: 486-493
2000 – 2009
- 2009
- [c3]Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco:
Event-driven gate-level simulation with GP-GPUs. DAC 2009: 557-562 - [c2]Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco:
GCS: High-performance gate-level simulation with GPGPUs. DATE 2009: 1332-1337 - [c1]Debapriya Chatterjee, Valeria Bertacco:
Activity-based refinement for abstraction-guided simulation. HLDVT 2009: 146-153
Coauthor Index
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