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Gilson I. Wirth
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2020 – today
- 2023
- [j23]Maurício Banaszeski da Silva
, Gilson I. Wirth
Random Telegraph Noise in Analog CMOS Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2229-2242 (2023) - 2021
- [c37]Gilson I. Wirth
Modeling and Simulation of Charge Trapping in 1/f Noise, RTN and BTI: from Devices to Circuits. MIXDES 2021: 14-19 - 2020
- [j22]Pablo Ilha Vaz, Gilson I. Wirth
TID effects on I-V characteristics of bulk CMOS STD and ELT-based devices in 600 nm. Microelectron. J. 97: 104722 (2020)
2010 – 2019
- 2018
- [j21]Pablo Ilha Vaz
Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library. J. Electron. Test. 34(6): 735-747 (2018) - [j20]Alexandre Simionovski, Gilson I. Wirth
A TCAD evaluation of a single Bulk-BICS with integrative memory cell. Microelectron. J. 80: 62-68 (2018) - [j19]Thiago Hanna Both, Gabriela Firpo Furtado
Modeling and simulation of the charge trapping component of BTI and RTS. Microelectron. Reliab. 80: 278-283 (2018) - [c36]Thales E. Becker, Fábio Fedrizzi Vidor
Time domain electrical characterization in zinc oxide nanoparticle thin-film transistors. LATS 2018: 1-6 - 2017
- [c35]Fábio Fedrizzi Vidor
Self-aligned ZnO nanoparticle-based TFTs for flexible electronics. AFRICON 2017: 644-648 - 2016
- [j18]Peterson R. Agostinho, Odair Lelis Goncalez
Rail to rail radiation hardened operational amplifier in standard CMOS technology with standard layout techniques. Microelectron. Reliab. 67: 99-103 (2016) - [c34]Raphael Martins Brum, Gilson I. Wirth
MagPDK: An open-source process design kit for circuit design with magnetic tunnel junctions. SBCCI 2016: 1-6 - 2015
- [j17]Alexandre Simionovski, Rafael Galhardo Vaz, Odair Lelis Goncalez
Impact of Total Ionizing Dose on Bulk Built-In Current Sensors with Dynamic Storage Cell. J. Electron. Test. 31(4): 411-417 (2015) - [j16]Felipe Rosa, Raphael Martins Brum, Gilson I. Wirth
Impact of dynamic voltage scaling and thermal factors on SRAM reliability. Microelectron. Reliab. 55(9-10): 1486-1490 (2015) - [j15]Alexandre Simionovski, Gilson I. Wirth
Adding a self-reset feature to the Bulk-BICS with dynamic storage cell. Microelectron. Reliab. 55(12): 2748-2753 (2015) - [c33]Felipe Rosa, Raphael Martins Brum, Gilson I. Wirth
Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability. ICECS 2015: 137-140 - [c32]Pablo Ilha Vaz, Alberto Wiltgen Junior, Gilson Inácio Wirth
Techniques for square ELT simulation: A comparative study. LASCAS 2015: 1-4 - 2014
- [j14]Fernanda Lima Kastensmidt
Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs. Microelectron. Reliab. 54(9-10): 2344-2348 (2014) - [j13]Vinicius V. A. Camargo, Ben Kaczer, Tibor Grasser, Gilson I. Wirth
Circuit simulation of workload-dependent RTN and BTI based on trap kinetics. Microelectron. Reliab. 54(11): 2364-2370 (2014) - [j12]Fábio Fedrizzi Vidor
Low temperature fabrication of a ZnO nanoparticle thin-film transistor suitable for flexible electronics. Microelectron. Reliab. 54(12): 2760-2765 (2014) - [j11]Vinicius V. A. Camargo, Ben Kaczer, Gilson I. Wirth
Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 280-285 (2014) - [c31]Fernanda Lima Kastensmidt
Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs. ETS 2014: 1-2 - [c30]Evaldo Carlos Fonseca Pereira, Odair Lelis Goncalez
The effects of total ionizing dose on the neutron SEU cross section of a 130 nm 4 Mb SRAM memory. LATW 2014: 1-4 - [c29]Alan Carlos Junior Rossetto, Gilson Inácio Wirth
Performance analysis of a clock generator PLL under TID effects. LATW 2014: 1-5 - 2013
- [c28]Dalton M. Colombo
Voltage reference design using 1 V power supply in 0.13 µm CMOS technology. LASCAS 2013: 1-4 - 2012
- [j10]Gilson I. Wirth
Compact modeling and simulation of Random Telegraph Noise under non-stationary conditions in the presence of random dopants. Microelectron. Reliab. 52(12): 2955-2961 (2012) - [c27]Ricardo Vanni Dallasen, Gilson Inácio Wirth
A PLL for clock generation with automatic frequency control under TID effects. SBCCI 2012: 1-5 - 2011
- [j9]Lucas Brusamarello, Gilson I. Wirth
Fast and accurate statistical characterization of standard cell libraries. Microelectron. Reliab. 51(12): 2341-2350 (2011) - [c26]Ulrich Hilleringmann
Semiconductor nanoparticles for electronic device integration on foils. AFRICON 2011: 1-6 - [c25]Miguel Miranda, Philippe Roussel, Lucas Brusamarello, Gilson I. Wirth
Statistical characterization of standard cells using design of experiments with response surface modeling. DAC 2011: 77-82 - 2010
- [c24]Dalton Martini Colombo
Design methodology using inversion coefficient for low-voltage low-power CMOS voltage reference. SBCCI 2010: 43-48 - [c23]Maurício Banaszeski da Silva
Modeling the impact of RTS on the reliability of ring oscillators. SBCCI 2010: 128-133
2000 – 2009
- 2009
- [j8]Lucas Brusamarello, Gilson I. Wirth
Statistical RTS model for digital circuits. Microelectron. Reliab. 49(9-11): 1064-1069 (2009) - [c22]Christian Jesús B. Fayomi, Gilson I. Wirth
An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation ADC in 0.18µm CMOS. ICECS 2009: 195-198 - [c21]Thiago Assis, Fernanda Lima Kastensmidt
Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies. LATW 2009: 1-6 - [c20]Franco Leite, Tiago R. Balen, Marcos Hervé, Marcelo Lubaszewski, Gilson I. Wirth
Using Bulk Built-In Current Sensors and recomputing techniques to mitigate transient faults in microprocessors. LATW 2009: 1-6 - [c19]Maurício Banaszeski da Silva
NBTI-aware technique for transistor sizing of high-performance CMOS gates. LATW 2009: 1-5 - [c18]Gustavo Neuberger, Gilson I. Wirth
Protecting digital circuits against hold time violation due to process variability. SBCCI 2009 - 2008
- [j7]Egas Henes Neto, Gilson I. Wirth
Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors. J. Electron. Test. 24(5): 425-437 (2008) - [j6]Gilson I. Wirth
Modeling the sensitivity of CMOS circuits to radiation induced single event transients. Microelectron. Reliab. 48(1): 29-36 (2008) - [j5]Gilson I. Wirth
Bulk built in current sensors for single event transient detection in deep-submicron technologies. Microelectron. Reliab. 48(5): 710-715 (2008) - [j4]Lucas Brusamarello, Roberto da Silva
Probabilistic Approach for Yield Analysis of Dynamic Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(8): 2238-2248 (2008) - [c17]Peter Glösekötter
Device degradation and resilient computing. ISCAS 2008: 828-831 - [c16]Christian Jesús B. Fayomi, Gilson I. Wirth
"The flipped voltage follower"-based low voltage fully differential CMOS sample-and-hold circuit. ISCAS 2008: 1716-1719 - 2007
- [j3]Gilson I. Wirth
Accurate and computer efficient modelling of single event transients in CMOS circuits. IET Circuits Devices Syst. 1(2): 137-142 (2007) - [j2]Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo Augusto da Luz Reis:
Técnicas probabilísticas para análise de yield em nível elétrico usando propagação de erros e derivadas numéricas. RITA 14(2): 69-89 (2007) - [c15]Dalton Martini Colombo
Impact of Noise on Trim Circuits for Bandgap Voltage References. ICECS 2007: 775-778 - [c14]Gilson I. Wirth
The Bulk Built In Current Sensor Approach for Single Event Transient Detection. SoC 2007: 1-4 - [c13]Lucas Brusamarello, Roberto da Silva
Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations. ISVLSI 2007: 86-91 - [c12]Carlos Arthur Lang Lisbôa, Fernanda Lima Kastensmidt
Using built-in sensors to cope with long duration transient faults in future technologies. ITC 2007: 1-10 - [c11]Dalton M. Colombo
Trim range limited by noise in bandgap voltage references. SBCCI 2007: 42-47 - [c10]Egas Henes Neto, Fernanda Lima Kastensmidt
A built-in current sensor for high speed soft errors detection robust to process and temperature variations. SBCCI 2007: 190-195 - [c9]Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth
Statistical and Numerical Approach for a Computer efficient circuit yield analysis. VLSI-SoC (Selected Papers) 2007: 1-24 - [c8]Gustavo Neuberger, Gilson I. Wirth
Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies. VLSI-SoC (Selected Papers) 2007: 1-16 - [c7]Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis, Gilson I. Wirth
Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies. VLSI-SoC 2007: 78-83 - [c6]Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth
Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level. VLSI-SoC 2007: 94-98 - 2006
- [j1]Egas Henes Neto, Ivandro Ribeiro, Michele G. Vieira, Gilson I. Wirth
Using Bulk Built-in Current Sensors to Detect Soft Errors. IEEE Micro 26(5): 10-18 (2006) - [c5]Gilson I. Wirth
Generation and Propagation of Single Event Transients in CMOS Circuits. DDECS 2006: 198-203 - [c4]Gilson I. Wirth
Single event transients in dynamic logic. SBCCI 2006: 184-189 - 2005
- [c3]Egas Henes Neto, Ivandro Ribeiro, Michele G. Vieira, Gilson I. Wirth, Fernanda Lima Kastensmidt:
Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic. SBCCI 2005: 62-67 - [c2]Gilson I. Wirth, Michele G. Vieira, Egas Henes Neto, Fernanda Gusmão de Lima Kastensmidt:
Single event transients in combinatorial circuits. SBCCI 2005: 121-126 - 2000
- [c1]Peter Glösekötter, Christian Pacha, Karl F. Goser, Gilson I. Wirth, Werner Prost, Uwe Auer, M. Agethen, P. Velling, Franz-Josef Tegude:
Digital Circuit Design Based on the Resonant-Tunneling-Hetero-Junction-Bipolar-Transistor. SBCCI 2000: 150-158
Coauthor Index
aka: Fernanda Gusmão de Lima Kastensmidt
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