default search action
MEMSYS 2021: Washington, DC, USA
- MEMSYS 2021: The International Symposium on Memory Systems, Washington, USA, September 27 - 30, 2021. ACM 2021, ISBN 978-1-4503-8570-1
- Xiaoming Du, Cong Li
:
Predicting Uncorrectable Memory Errors from the Correctable Error History: No Free Predictors in the Field. 1:1-1:10 - Mohamed Assem Ibrahim
Efficient Cache Utilization via Model-aware Data Placement for Recommendation Models. 2:1-2:11 - Thomas Vogelsang, Brent Haukness, Eric Linstadt, Torsten Partsch, James Tringali:
DRAM Refresh with Master Wordline Granularity Control of Refresh Intervals: Position Paper. 3:1-3:6 - Reza Mirosanlou, Mohamed Hassan
DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance. 4:1-4:16 - Diego Moura, Vinicius Petrucci, Daniel Mossé:
Learning to Rank Graph-based Application Objects on Heterogeneous Memories. 5:1-5:14 - Thaleia Dimitra Doudali, Ada Gavrilovska:
Toward Computer Vision-based Machine Intelligent Hybrid Memory Management. 6:1-6:6 - Luyi Kang, Bruce L. Jacob:
Zoned FTL: Achieve Resource Isolation via Hardware Virtualization. 7:1-7:8 - Manaal Mukhtar Jamadar, Jaspinder Kaur
MAPCP: Memory Access Pattern Classifying Prefetcher. 8:1-8:12 - Oliver Lenke, Richard Petri, Thomas Wild, Andreas Herkersdorf:
PEPERONI: Pre-Estimating the Performance of Near-Memory Integration. 9:1-9:6 - Wesley Smith, Daniel Byrne, Chen Ding:
Writeback Modeling: Theory and Application to Zipfian Workloads. 10:1-10:14 - L. J. Gokul Vasan, Éder F. Zulian, Christian Weis, Matthias Jung, Norbert Wehn:
Online Working Set Change Detection with Constant Complexity: The Cornerstone for Memory Management Algorithms in Scalable Systems. 11:1-11:16 - Lukas Steiner, Kira Kraft, Denis Uecker, Matthias Jung, Michael Huonker, Norbert Wehn:
An LPDDR4 Safety Model for Automotive Applications. 12:1-12:9 - Amit Berman
Low-Latency Modulation Scheme for Solid State Drive. 13:1-13:6 - Ivy Peng, Ian Karlin, Maya B. Gokhale, Kathleen Shoga, Matthew P. LeGendre, Todd Gamblin:
A Holistic View of Memory Utilization on HPC Systems: Current and Future Trends. 14:1-14:11 - Jin Wu
WDBT: Wear Characterization, Reduction, and Leveling of DBT Systems for Non-Volatile Memory. 15:1-15:13
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-19 22:02 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: