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ISPD 2020: Taipei, Taiwan
- William Swartz, Jens Lienig:
ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29 - April 1, 2020, delayed to September 20-23, 2020. ACM 2020, ISBN 978-1-4503-7091-2
Keynote 1
- Ivo Bolsens:
Scalable System and Silicon Architectures to Handle the Workloads of the Post-Moore Era. 1-2
Session 1: Placement
- Anna Goldie, Azalia Mirhoseini:
Placement Optimization with Deep Reinforcement Learning. 3-7 - Mohammad T. Khasawneh, Patrick H. Madden:
Hill Climbing with Trees: Detail Placement for Large Windows. 9-16 - Yong Zhong, Tao-Chun Yu, Kai-Chuan Yang, Shao-Yun Fang:
Via Pillar-aware Detailed Placement. 17-24 - Dimitrios Mangiras, Pavlos M. Mattheakis, Pierre-Olivier Ribet, Giorgos Dimitrakopoulos:
Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV. 25-32
Session 2: Breaking New Ground: From Carbon Nanotubes to Packaging
- Gage Hills, Christian Lau, Tathagata Srimani
, Mindy D. Bishop, Pritpal Kanhaiya, Rebecca Ho, Aya G. Amer, Max M. Shulaker:
Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V Microprocessor. 33-38 - Lingjun Zhu
Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs. 39-46 - Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim
Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs. 47-54
Session 3: Machine Learning for Physical Design (part 1)
- Kishor Kunal
Learning from Experience: Applying ML to Analog Circuit Design. 55 - Wei-Tse Hung, Jun-Yang Huang, Yih-Chih Chou, Cheng-Hong Tsai, Mango Chia-Tso Chao:
Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network. 57-64 - Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng:
Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning. 65-72
Keynote 2
- Cliff Hou:
Physical Design for 3D Chiplets and System Integration. 73
Session 4: Circuit Design and Security
- Johann Knechtel:
Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges. 75-86 - Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos
Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation. 87-94 - Hao-Chun Chang, Li-An Huang, Kai-Chiang Wu, Yu-Guang Chen:
Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience. 95-102
Session 5: Timing and Clocking
- Necati Uysal
Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current. 103-110 - Sin-Hong Liou, Sean S.-Y. Liu, Richard Sun, Hung-Ming Chen:
Timing Driven Partition for Multi-FPGA Systems with TDM Awareness. 111-118
Session 6: Machine Learning for Physical Design (part 2)
- Yuzhe Ma, Zhuolun He, Wei Li, Lu Zhang, Bei Yu:
Understanding Graphs in EDA: From Shallow to Deep Learning. 119-126 - Wei Ye, Mohamed Baker Alawieh, Yuki Watanabe, Shigeki Nojima, Yibo Lin, David Z. Pan:
TEMPO: Fast Mask Topography Effect Modeling with Deep Learning. 127-134 - Rongjian Liang
DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network. 135-142
Keynote 3
- Juan C. Rey:
Physical Verification at Advanced Technology Nodes and the Road Ahead. 143
Session 8: ISPD 2020 Contest Results and Poster Presentations
- Michael James, Marvin Tom, Patrick Groeneveld, Vladimir Kibardin:
ISPD 2020 Physical Mapping of Neural Networks on a Wafer-Scale Deep Learning Accelerator. 145-149
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