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ISVLSI 2020: Limassol, Cyprus
- 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020, Limassol, Cyprus, July 6-8, 2020. IEEE 2020, ISBN 978-1-7281-5775-7
CRT - I
- Mounika Kelam, Balaji Yadav Battu, Zia Abbas
:
A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation Oscillator. 1-6 - Ahmad Tarraf
Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets. 7-12 - Smrutilekha Samanta
A 1.8V 8-Bit 500 MSPS Segmented Current Steering DAC with >66 dB SFDR. 13-17
CAD - I
- Halima Najibi, Jorge Hunter, Alexandre Levisse, Marina Zapater, Miroslav Vasic, David Atienza:
Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters. 18-23 - Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. 24-29 - Marcos T. Leipnitz, Murilo R. Perleberg
Enhancing Real-Time Motion Estimation through Approximate High-Level Synthesis. 30-35 - Ioannis Galanis, Iraklis Anagnostopoulos, Chinh Nguyen, Guillermo Bares, Dona Burkard:
Inference and Energy Efficient Design of Deep Neural Networks for Embedded Devices. 36-41
DCF - I
- Amin Norollah
3D-Sorter: 3D Design of a Resource-Aware Hardware Sorter for Edge Computing Platforms Under Area and Energy Consumption Constraints. 42-47 - Suraj Dohar, Siddharth R. K.
A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications. 48-53 - Ameer Shalabi, Kolin Paul, Tara Ghasempouri
NV-SP: A New High Performance and Low Energy NVM-Based Scratch Pad. 54-59
EPT - I
- Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann
2-Output Spin Wave Programmable Logic Gate. 60-65 - Marcel Walter
Bail on Balancing: An Alternative Approach to the Physical Design of Field-Coupled Nanocomputing Circuits. 66-71 - Baogang Zhang
Fast Resilient-Aware Data Layout Organization for Resistive Computing Systems. 72-77
DCF - II
- Gopal Raut
A CORDIC Based Configurable Activation Function for ANN Applications. 78-83 - Raunaq Nayar
Hardware Optimized Approximate Adder with Normal Error Distribution. 84-89 - Yirong Kan, Man Wu
A Multi-grained Reconfigurable Accelerator for Approximate Computing. 90-95 - Mohammadreza Esmali Nojehdeh, Levent Aksoy
Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks. 96-101
SDS - I
- Seungseok Nam, Emil Matús, Sadia Moriam, Gerhard P. Fettweis:
Path-Spreading Search Algorithm and ASIP Approach for Connection Allocation in TDM-NoCs. 102-107 - Vinay C. Patil, Sandip Kundu:
On Leveraging Multi-threshold FinFETs for Design Obfuscation. 108-113 - Michaela Brunner, Michael Gruber, Michael Tempelmeier
Logic Locking Induced Fault Attacks. 114-119 - Nourhan Elhamawy, Maël Gay, Ilia Polian:
An Open-Source Area-Optimized ECEG Cryptosystem in Hardware. 120-125
QCW - I
- Oumarou Oumarou, Alexandru Paler
QUANTIFY: A Framework for Resource Analysis and Design Verification of Quantum Circuits. 126-131 - Giovanni Amedeo Cirillo, Giovanna Turvani
Advances in Molecular Quantum Computing: from Technological Modeling to Circuit Design. 132-137 - Thomas Ayral, François-Marie Le Régent, Zain H. Saleem
Quantum Divide and Compute: Hardware Demonstrations and Noisy Simulations. 138-140 - Shaun Miller:
Quantum Resource Counts for Operations Constructed from an Addition Circuit. 141-146 - Abhijit Das
Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors. 147-152
SDS - II
- Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption. 153-159 - Subodha Charles, Prabhat Mishra
Lightweight and Trust-Aware Routing in NoC-Based SoCs. 160-167 - Subodha Charles, Prabhat Mishra
Securing Network-on-Chip Using Incremental Cryptography. 168-175
Student Research Forum
- Marcel Walter
Design Automation for Field-Coupled Nanotechnologies. 176-181 - Vladimir Herdt, Rolf Drechsler
Efficient Techniques to Strongly Enhance the Virtual Prototype Based Design Flow. 182-187 - Mehran Goli
Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization. 188-193 - Sukarn Agarwal
LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors. 194-199
CRT - II
- Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya:
Locating Open-Channels in Octagon Networks on Chip-Microprocessors. 200-205 - Chenhui Feng, Hui Qian, Zhongfeng Wang:
An Implementation of Pre-Quantized Random Demodulator Based on Amplitude-to-Pulse Converter. 206-211 - Prema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi:
A 2^7 -1 Low-Power Half-Rate 16-Gb/s Charge-Mode PRBS Generator in 1.2V, 65nm CMOS. 212-215
SDS - III
- Mahdi Zahedi, Mahta Mayahinia, Muath Abu Lebdeh
Efficient Organization of Digital Periphery to Support Integer Datatype for Memristor-Based CIM. 216-221 - Shashank Suman, Hemangee K. Kapoor:
Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache. 222-227 - Yaohua Wang, Xiaowen Chen, Xiao Hu:
Associative Thread Compaction for Efficient Control Flow Handling in GPGPUs. 228-233
AFC - I
- Anthony Bisulco, Fernando Cladera Ojeda
Near-Chip Dynamic Vision Filtering for Low-Bandwidth Pedestrian Detection. 234-239 - Saurabh Tewari
Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators. 240-245 - Junseok Oh, Florian Neugebauer, Ilia Polian, John P. Hayes:
Retraining and Regularization to Optimize Neural Networks for Stochastic Computing. 246-251 - Margherita Ronchini, Milad Zamani
Tunable Voltage-Mode Subthreshold CMOS Neuron. 252-257 - Bokyung Kim, Hai Li:
Leveraging 3D Vertical RRAM to Developing Neuromorphic Architecture for Pattern Classification. 258-263
Special Session: Secure and High-Speed Electronic Systems - I
- Ibrahim L. Olokodana, Saraju P. Mohanty, Elias Kougianos:
Distributed Kriging-Bootstrapped DNN Model for Fast, Accurate Seizure Detection from EEG Signals. 264-269 - Sheikh Ariful Islam
SafeController: Efficient and Transparent Control-Flow Integrity for RTL Design. 270-275 - Liuting Shang, Muhammad Adil, Ramtin Madani, Chenyun Pan:
Fast Linear Programming Optimization Using Crossbar-Based Analog Accelerator. 276-281
QCW - II
- Daniel Vert, Renaud Sirdey
Operational Quantum Annealers are Cursed by their Qubits Interconnection Topologies. 282-287 - Teruo Tanimoto
How Many Trials Do We Need for Reliable NISQ Computing? 288-290 - Teruo Tanimoto
Practical Error Modeling Toward Realistic NISQ Simulation. 291-293 - Suvadip Batabyal, Lovekush Sharma:
A Quantum Pipeline for an Executable Quantum Instruction Set Architecture. 294-299
Special Session: Secure and High-Speed Electronic Systems - II
- Yuwen Cui, Shakthi Prabhakar, Hui Zhao, Saraju P. Mohanty, Juan Fang:
A Low-Cost Conflict-Free NoC Architecture for Heterogeneous Multicore Systems. 300-305 - Juan Fang, Jiaxing Zhang, Shuaibing Lu, Hui Zhao:
Exploration on Task Scheduling Strategy for CPU-GPU Heterogeneous Computing System. 306-311 - Wu Yang, Himanshu Thapliyal
Low-Power and Energy-Efficient Full Adders With Approximate Adiabatic Logic for Edge Computing. 312-315
CRT - III
- Christos Georgakidis, Christos P. Sotiriou, Nikolaos Sketopoulos, Milos Krstic
R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints. 316-321 - Farzane Rabiee, Mostafa Kajouyan, Newsha Estiri, Jordan Fluech, Mahdi Fazeli, Ahmad Patooghy:
Enduring Non-Volatile L1 Cache Using Low-Retention-Time STTRAM Cells. 322-327 - Joseph Paturel, Angeliki Kritikakou
Fast Cross-Layer Vulnerability Analysis of Complex Hardware Designs. 328-333
DCF - III
- Bo Wu, Jing Tian, Xiao Hu, Zhongfeng Wang:
A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography. 334-339 - Shao-I Chu, Chen-En Hsieh, Yi-Ming Lee, Sayed Ahmad Salehi:
Enhanced Architecture for Computing Polynomials Using Unipolar Stochastic Logic. 340-345 - Ricardo Coelho, Felipe Tanus, Álvaro F. Moreira, Gabriel L. Nazar:
ACQuA: A Parallel Accelerator Architecture for Pure Functional Programs. 346-351 - Weihang Tan, Antian Wang, Yunhao Xu, Yingjie Lao:
Area-Efficient Pipelined VLSI Architecture for Polar Decoder. 352-357
Poster Session I
- Selahattin Sayil, Subed Lamichhane, Kutay Sayil:
Coupling Noise Mitigation using a Pass Transistor. 358-362 - Jitumani Sarma, Shatadal Chatterjee, Rakesh Biswas
A Fast Transient Digitally Assisted Flash-Based Modular LDO for Sensor Nodes in WBAN. 363-367 - Andreas Kouloumpris, Theocharis Theocharides, Maria K. Michael:
Cost-Effective Time-Redundancy Based Optimal Task Allocation for the Edge-Hub-Cloud Systems. 368-373 - Mahboube Fakhire, Ali Jahanian:
Vulnerability Analysis Against Fault Attack in terms of the Timing Behavior of Fault Injection. 374-379 - Josie E. Rodriguez Condia
Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets. 380-385 - Tiankai Su, Atif Yasin, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach. 386-391 - Stavros Simoglou, Christos P. Sotiriou, Dimitris Valiantzas, Nikolaos Sketopoulos:
STA for Mixed Cyclic, Acyclic Circuits. 392-397 - Nikolaos Sketopoulos, Christos P. Sotiriou, Vasilis F. Pavlidis:
Metal Stack and Partitioning Exploration for Monolithic 3D ICs. 398-403 - Yuan-Dar Chung, Rung-Bin Lin:
Engineering a Standard Cell Library for an Industrial Router with ASAP7 PDK. 404-409 - Yongwen Zhuang, Dongmei Li:
Real Time Bayer Raw Video Projective Transformation System Using FPGA. 410-414 - Khyati Kiyawat
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. 415-421 - Sayed Ahmad Salehi, Durjoy Deb Dhruba
Efficient Hardware Implementation of Discrete Wavelet Transform Based on Stochastic Computing. 422-427 - Jianchi Sun, Nikhilesh Sharma, Jacob Chakareski, Nicholas Mastronarde, Yingjie Lao:
Action Evaluation Hardware Accelerator for Next-Generation Real-Time Reinforcement Learning in Emerging IoT Systems. 428-433 - Alish Kanani
ACA-CSU: A Carry Selection Based Accuracy Configurable Approximate Adder Design. 434-439
Special Session : IoT based Consumer Technologies for Smart Cities
- Amit Mahesh Joshi, Prateek Jain
Secure-iGLU: A Secure Device for Noninvasive Glucose Measurement and Automatic Insulin Delivery in IoMT Framework. 440-445 - Ahmad Alkhodair
McPoRA: A Multi-chain Proof of Rapid Authentication for Post-Blockchain Based Security in Large Scale Complex Cyber-Physical Systems. 446-451 - Abraham Peedikayil Kuruvila, Shamik Kundu, Kanad Basu:
Analyzing the Efficiency of Machine Learning Classifiers in Hardware-Based Malware Detectors. 452-457 - Saswat Kumar Ram
A Solar Based Power Module for Battery-Less IoT Sensors Towards Sustainable Smart Cities. 458-463
Special Session on EU Projects
- Christos P. Antonopoulos, Georgios Keramidas, Vassilis Tsakanikas, Evi Faliagka, Christos Panagiotou
Capacity Building Among European Stakeholders In the Areas of Cyber-Physical Systems, IoT & Embedded Systems: The SMART4ALL Digital Innovation Hub Perspective. 464-469 - Georgios Keramidas, Christos P. Antonopoulos, Nikolaos S. Voros
CPSoSaware: Cross-Layer Cognitive Optimization Tools & Methods for the Lifecycle Support of Dependable CPSoS. 470-475 - Christos Kyrkou
Towards Artificial-Intelligence-Based Cybersecurity for Robustifying Automated Driving Systems Against Camera Sensor Attacks. 476-481
EPT - II
- Lulu Ge, Keshab K. Parhi
Molecular MUX-Based Physical Unclonable Functions. 482-487 - Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. 488-493 - Manobendra Nath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Current Comparator-Based Reconfigurable Adder and Multiplier on Hybrid Memristive Crossbar. 494-499
SDS - IV
- Christoph Frisch, Michael Tempelmeier
PAG-IoT: A PUF and AEAD Enabled Trusted Hardware Gateway for IoT Devices. 500-505 - Yanming Zhang, Xu Qiu, Qin Li, Fei Qiao, Qi Wei, Li Luo, Huazhong Yang:
Optimization and Evaluation of Energy-Efficient Mixed-Signal MFCC Feature Extraction Architecture. 506-511 - Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi:
A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. 512-517
Poster Session II
- Keshav Govindarajan, V. S. Kanchana Bhaaskaran
Borrow Select Subtractor for Low Power and Area Efficiency. 518-523 - Md. Adnan Zaman, Rajeev Joshi, Srinivas Katkoori
High Level Modeling of Memristive Crossbar Arrays. 524-529 - Bastian Richter, Amir Moradi
Lightweight Ciphers on a 65 nm ASIC A Comparative Study on Energy Consumption. 530-535 - Cezar Reinbrecht
Guard-NoC: A Protection Against Side-Channel Attacks for MPSoCs. 536-541 - Tuhin Subhra Das, Navonil Chatterjee, Prasun Ghosal:
Regulating Degree of Adaptiveness for Performance-Centric NoC Routing. 542-547 - Boqian Wang, Zhonghai Lu:
Supporting QoS in AXI4 Based Communication Architecture. 548-553 - Jun Zhou, Mengquan Li, Pengxing Guo, Weichen Liu:
Mitigation of Tampering Attacks for MR-Based Thermal Sensing in Optical NoCs. 554-559 - Ioannis Zografopoulos
DERauth: A Battery-Based Authentication Scheme for Distributed Energy Resources. 560-567 - Rakesh Kumar, Bibhas Ghoshal:
Classification and Workload Balancing of Multi-threaded Application on Embedded Platforms. 568-573 - Nandan Kumar Jha, Shreyas Ravishankar, Sparsh Mittal, Arvind Kaushik, Dipan Mandal, Mahesh Chandra
DRACO: Co-Optimizing Hardware Utilization, and Performance of DNNs on Systolic Accelerator. 574-579 - Hui Zhang, Wei Wu, Yufei Ma, Zhongfeng Wang:
Efficient Hardware Post Processing of Anchor-Based Object Detection on FPGA. 580-585 - Eric Homan, Chonghan Lee, Jack Sampson, John P. Sustersic, Vijaykrishnan Narayanan
DoubtNet: Using Semantic Context to Enable Adaptive Inference for the IoT. 586-591 - Nagadastagiri Challapalle, Makesh Chandran, Sahithi Rampalli, Vijaykrishnan Narayanan:
X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization. 592-597
Research Demo
- Amit Mahesh Joshi, Prateek Jain
iGLU: Non-Invasive Device for Continuous Glucose Measurement with IoMT Framework. 598-599 - Alhagie Sallah, Prabha Sundaravadivel:
Tot-Mon: A Real-Time Internet of Things Based Affective Framework for Monitoring Infants. 600-601 - Tyler Cultice, Carson Labrado, Himanshu Thapliyal
A PUF Based CAN Security Framework. 602-603
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