default search action
12th IOLTS 2006: Como, Italy
- 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy. IEEE Computer Society 2006, ISBN 0-7695-2620-9
Keynote Talk
- Andrea Cuomo:
The Challenge of Reliability in Future Complex Systems. 3
Invited Talk
- Norbert Seifert:
Extending Moore's Law into the next Decade - the SER Challenge. 7
Session 1: Fault Effects and Self-Checking Techniques
- Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache, Stéphane Rossignol, Pascal Moitrel:
Characterizing Laser-Induced Pulses in ICs: Methodology and Results. 11-16 - Cecilia Metra, Martin Omaña, Daniele Rossi
, José Manuel Cazeaux, T. M. Mak:
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. 17-22 - Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel:
A New Self-Checking and Code-Disjoint Non-Restoring Array Divider. 23-30
Session 2: BIST Techniques
- Swaroop Ghosh, Swarup Bhunia
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. 31-36 - Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST. 37-42 - Stelios Neophytou
Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding. 43-50
Session 3: Technology Robustness
- G. Cellere, Alessandro Paccagnella
Erratic Effects of Irradiation in Floating Gate Memory Cells. 51-56 - Tino Heijmen, Damien Giot, Philippe Roche:
Factors That Impact the Critical Charge of Memory Elements. 57-62 - Guillaume Hubert
Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic Cells. 63-74
Special Session 1: Memory Reliability Challenges
- Robert C. Aitken:
Reliability Issues for Embedded SRAM at 90nm and Below. 75 - Rochit Rajsuman:
Towards The Methodology of On-line Diagnosis. 76
Special Session 2: Test and Reliability Challenges for Innovative Systems
- T. M. Mak:
Test Challenges for 3D Circuits. 79 - Marcello Coppola
Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication Network. 80 - Magdy S. Abadir:
Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs. 81 - Isaac Levendel:
The Consequences of Variability in Software. 82
Panel 1
- Lorena Anghel, Michael Nicolaidis, Nadine Buard:
From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately? 85
Embedded Tutorials: Innovative Design for Robustness
- Melanie Berg:
Fault Tolerance Implementation within SRAM Based FPGA Design Based upon the Increased Level of Single Event Upset Susceptibility. 89-91 - Marc Renaudin, Yannick Monnet:
Asynchronous Design: Fault Robustness and Security Characteristics. 92-95
Session 4: Soft Errors and Latchup Mitigation
- André K. Nieuwland, Samir Jasarevic, Goran Jerin:
Combinational Logic Soft Error Analysis and Protection. 99-104 - Sandip Kundu, Ilia Polian:
An Improved Technique for Reducing False Alarms Due to Soft Errors. 105-110 - Michael Nicolaidis:
A Low-Cost Single-Event Latchup Mitigation Sscheme. 111-118
Session 5: Secure Circuits
- David Hély
Secure Scan Techniques: A Comparison. 119-124 - Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet:
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. 125-130 - Konrad J. Kulikowski, Mark G. Karpovsky, Alexander Taubin:
Power Attacks on Secure Hardware Based on Early Propagation of Data. 131-138
Session 6: Fault Detection Techniques
- Maico Cassel, Fernanda Lima Kastensmidt
Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs. 139-144 - Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande:
On-line Fault Detection and Location for NoC Interconnects. 145-150 - Ramtilak Vemu, Jacob A. Abraham:
CEDA: Control-flow Error Detection through Assertions. 151-158
Session 7: Analog Circuits Dependability
- Vishwanath Natarajan, Ganesh Srinivasan, Abhijit Chatterjee:
On-Line Error Detection in Wireless RF Transmitters Using Real-time Streaming Data. 159-164 - Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel
Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study. 165-172
Session 8: Posters
- Steffen Tarnick:
Embedded Borden 2-UED Code Checkers. 173-175 - Luca Breveglieri, Paolo Maistri, Israel Koren:
A Note on Error Detection in an RSA Architecture by Means of Residue Codes. 176-177 - Gian Carlo Cardarilli
Localization of Faults in Radix-n Signed Digit Adders. 178-180 - Christian Galke, René Kothe, Sabine Schultke, K. Winkler, Jeanette Honko, Heinrich Theodor Vierhaus:
Embedded Scan Test with Diagnostic Features for Self-Testing SoCs. 181-182 - Mario García-Valderas
Emulation-based Fault Injection in Circuits with Embedded Memories. 183-184 - Pavel Kubalík, Petr Fiser, Hana Kubátová:
Fault Tolerant System Design Method Based on Self-Checking Circuits. 185-186 - S. Habermann, René Kothe, Heinrich Theodor Vierhaus:
Built-in Self Repair by Reconfiguration of FPGAs. 187-188 - Luca Sterpone
Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices. 189-190 - Arthur Pereira Frantz, Luigi Carro
Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers. 191-192 - Dimitris Nikolos, Dimitrios Kagaris, Spyros Gidaros:
Diophantine-Equation Based Arithmetic Test Set Embedding. 193-194 - Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt
Design of a Robust 8-Bit Microprocessor to Soft Errors. 195-196
Panel 2
- T. M. Mak, Subhasish Mitra:
Should Logic SER be Solved at the Circuit Level? 199
Session 9: Reliable Systems
- Michel Pignol:
DMT and DT2: Two Fault-Tolerant Architectures developed by CNES for COTs-based Spacecraft Supercomputers. 203-212 - Riccardo Mariani, Peter Fuhrmann, Boris Vittorelli:
Fault-Robust Microcontrollers for Automotive Applications. 213-218 - Jacques Henri Collet, Piotr Zajac
Contribution of Communications to Dependability in Massively-Defective General-Purpose Nanoarchitectures. 219-228
Session 10: Dependability Analysis
- Matteo Sonza Reorda
Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems. 229-234 - P. Kenterlis, Nektarios Kranitis
A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs. 235-241 - André V. Fidalgo
Real Time Fault Injection Using a Modified Debugging Infrastructure. 242-250
Session 11: New Topics in Fault Detection
- Alexander V. Drozd, M. V. Lobachev, Julia V. Drozd:
The Problem of On-Line Testing Methods In Approximate Data Processing. 251-256 - Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina
Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes. 257-262 - Deepali Koppad
Online Testing by Protocol Decomposition. 263-268
Special Session 3: SER Trends: Vision and Developments from European IDMs
- Tino Heijmen:
Soft Error Rates in Deep-Submicron CMOS Technologies. 271 - Günter Schindlbeck:
Trend in DRAM Soft Errors. 272
Session 12: Checkers and Error Correction
- Daniele Rossi
Checker No-Harm Alarm Robustness. 275-280 - Frederic Worm, Patrick Thiran, Paolo Ienne:
Designing Robust Checkers in the Presence of Massive Timing Errors. 281-286 - Petros Oikonomakos, Paul Fox:
Error Correction in Arithmetic Operations by I/O Inversion. 287-292
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-26 00:35 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: