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ACM Great Lakes Symposium on VLSI 2022: Irvine, CA, USA
- Ioannis Savidis, Avesta Sasan, Himanshu Thapliyal, Ronald F. DeMara:
GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022. ACM 2022, ISBN 978-1-4503-9322-5
Keynote I: Andrew Kahng
- Andrew B. Kahng:
AI/ML, Optimization and EDA in the TILOS AI Research Institute. 1
Session 1A: Hardware Security
- Kris Gaj:
Session details: Session 1A: Hardware Security. - Pantea Kiaei, Zhenyuan Liu, Patrick Schaumont
:
Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment. 3-8 - Tianhong Xu, Cheng Gongye, Yunsi Fei:
Protected ECC Still Leaks: A Novel Differential-Bit Side-channel Power Attack on ECDH and Countermeasures. 9-14 - Kalle Ngo, Elena Dubrova:
Side-Channel Analysis of the Random Number Generator in STM32 MCUs. 15-20 - Farah Ferdaus, Bashir Mohammad Sabquat Bahar Talukder, Md. Tauhidur Rahman:
Watermarked ReRAM: A Technique to Prevent Counterfeit Memory Chips. 21-26
Session 1B: Emerging Computing and Post-CMOS Technologies
- Deliang Fan:
Session details: Session 1B: Emerging Computing and Post-CMOS Technologies. - Zhangying He, Amin Rezaei, Houman Homayoun, Hossein Sayadi:
Deep Neural Network and Transfer Learning for Accurate Hardware-Based Zero-Day Malware Detection. 27-32 - Kangqiang Pan, Amr M. S. Tosson, Ningxuan Wang, Norman Y. Zhou
A Novel 2T2R CR-based TCAM Design for High-speed and Energy-efficient Applications. 33-38 - Amitesh Sridharan, Fan Zhang
MnM: A Fast and Efficient Min/Max Searching in MRAM. 39-44 - Yadu Kiran, Marc D. Riedel
A Scalable, Deterministic Approach to Stochastic Computing. 45-51
Session 2A: Hardware Security
- Kris Gaj:
Session details: Session 2A: Hardware Security. - Guangwei Zhao
Graph Neural Network based Netlist Operator Detection under Circuit Rewriting. 53-58 - Anupam Golder
Exploration into the Explainability of Neural Network Models for Power Side-Channel Analysis. 59-64 - Shien Zhu
iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations. 65-70 - Mengqiang Lu, Aijiao Cui, Yan Shao, Gang Qu:
A Memristor-based Secure Scan Design against the Scan-based Side-Channel Attacks. 71-76
Session 2B: Computer-Aided Design (CAD)
- Emre Salman:
Session details: Session 2B: Computer-Aided Design (CAD). - Dimitrios Garyfallou
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance. 77-83 - M. Imtiaz Rashid, Benjamin Carrion Schafer:
Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration. 85-90 - Sethu Jose, John Sampson, Vijaykrishnan Narayanan, Mahmut Taylan Kandemir:
A Scheduling Framework for Decomposable Kernels on Energy Harvesting IoT Edge Nodes. 91-96 - Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing. 97-103
Poster Overview 1
- Gaurav Kumar
On Attacking Locking SIB based IJTAG Architecture. 105-109 - Brooks Olney, Robert Karam:
Protecting Deep Neural Network Intellectual Property with Architecture-Agnostic Input Obfuscation. 111-115 - Manoj Gopale, Gregory Ditzler, Roman Lysecky, Janet Roveda:
Inter-Architecture Portability of Artificial Neural Networks and Side Channel Attacks. 117-121 - Gagan Gayari, Chandan Karfa, Prithwijit Guha:
GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking. 123-126 - Raheel Afsharmazayejani, Hossein Sayadi, Amin Rezaei:
Distributed Logic Encryption: Essential Security Requirements and Low-Overhead Implementation. 127-131 - Kaveh Shamsi, Guangwei Zhao
An Oracle-Less Machine-Learning Attack against Lookup-Table-based Logic Locking. 133-137 - Amin Sarihi, Ahmad Patooghy, Peter Jamieson, Abdel-Hameed A. Badawy:
Hardware Trojan Insertion Using Reinforcement Learning. 139-142 - Tolulope A. Odetola, Faiq Khalid, Syed Rafay Hasan:
LaBaNI: Layer-based Noise Injection Attack on Convolutional Neural Networks. 143-146 - Armin Darjani, Nima Kavand, Shubham Rai
ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks. 147-151 - Sanket Shukla, Gaurav Kolhe, Houman Homayoun, Setareh Rafatirad, Sai Manoj P. D.:
RAFeL - Robust and Data-Aware Federated Learning-inspired Malware Detection in Internet-of-Things (IoT) Networks. 153-157 - Khitam M. Alatoun, Ranga Vemuri:
Efficient Method for Timing-based Information Flow Verification in Hardware Designs. 159-163 - Zhongdong Qi, Jingchong Zhang, Gengjie Chen, Hailong You:
Effective and Efficient Detailed Routing with Adaptive Rip-up Scheme and Pin Access Refinement. 165-168 - Zhaoqi Fu, Wenxin Yu, Jie Ma, Xin Cheng:
An Efficient Maze Routing Algorithm for Fast Global Routing. 169-172 - Jie Ma, Wenxin Yu, Zhaoqi Fu, Xin Cheng:
Optimal Region-based Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints. 173-176 - Myong Kong, Daeyeon Kim, Minhyuk Kweon, Seokhyeong Kang:
GAN-Dummy Fill: Timing-aware Dummy Fill Method using GAN. 177-181 - Lucas Klemmer
RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V. 183-187 - Prashanth H. C.
Evolutionary Standard Cell Synthesis of Unconventional Designs. 189-192 - Pascal Pieper
Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype. 193-197 - Varun Bhatnagar, Gopal Raut
Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array. 199-202
Keynote II: Kaushik Roy
- Kaushik Roy:
In-Memory Computing based Machine Learning Accelerators: Opportunities and Challenges. 203-204
Session 3A: VLSI Design + VLSI Circuits and Power Aware Design 1
- Saraju P. Mohanty:
Session details: Session 3A: VLSI Design + VLSI Circuits and Power Aware Design 1. - Kamil Khan, Sudeep Pasricha, Ryan Gary Kim:
RACE: A Reinforcement Learning Framework for Improved Adaptive Control of NoC Channel Buffers. 205-210 - Rose George Kunthara
DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks. 211-216 - N. S. Aswathy, Sreesiddesh Bhavanasi, Arnab Sarkar, Hemangee K. Kapoor:
SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories. 217-222 - Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza:
Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays. 223-228
Session 3B: VLSI for Machine Learning and Artifical Intelligence 1
- Jingtong Hu:
Session details: Session 3B: VLSI for Machine Learning and Artifical Intelligence 1. - Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the Edge. 229-235 - Hang Xiao, Haobo Xu, Xiaoming Chen, Yujie Wang, Yinhe Han:
P3S: A High Accuracy Probabilistic Prediction Processing System for CNN Acceleration. 237-242 - Tianyang Yu
Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy. 243-248 - Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza:
Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge. 249-254
Session 4A: Testing, Reliability and Fault Tolerance
- Mark Zwolinski:
Session details: Session 4A: Testing, Reliability and Fault Tolerance. - Aibin Yan, Zhen Zhou, Shaojie Wei, Jie Cui, Yong Zhou, Tianming Ni, Patrick Girard, Xiaoqing Wen:
A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology. 255-260 - Aibin Yan, Zhihui He, Jing Xiang, Jie Cui, Yong Zhou, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications. 261-266 - Moisés Herrera, Peter A. Beerel
Radiation Hardening by Design Techniques for the Mutual Exclusion Element. 267-273 - Wei Xiong
An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique. 275-280
Session 4B: VLSI for Machine Learning and Artifical Intelligence 2
- Jingtong Hu:
Session details: Session 4B: VLSI for Machine Learning and Artifical Intelligence 2. - Arpan Dutta, Saransh Gupta, Behnam Khaleghi, Rishikanth Chandrasekaran, Weihong Xu, Tajana Rosing:
HDnn-PIM: Efficient in Memory Design of Hyperdimensional Computing with Feature Extraction. 281-286 - Jiaqi Yang, Hao Zheng, Ahmed Louri:
Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation. 287-292 - Wanqian Li, Yinhe Han, Xiaoming Chen:
Energy-Efficient In-SRAM Accumulation for CMOS-based CNN Accelerators. 293-298 - Jun Zeng, Mingyang Kou
KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference. 299-304
Poster Overview 2
- Suryansh Upadhyay, Abdullah Ash-Saki, Rasit Onur Topaloglu
A Shuttle-Efficient Qubit Mapper for Trapped-Ion Quantum Computers. 305-308 - Abdulqader Nael Mahmoud, Nicoleta Cucu Laurenciu, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana
Would Magnonic Circuits Outperform CMOS Counterparts? 309-313 - Ziying Cui, Ke Chen, Bi Wu, Chenggang Yan, Weiqiang Liu:
An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits. 315-318 - Md Hasibul Amin, Mohammed E. Elbtity, Mohammadreza Mohammadi, Ramtin Zand:
MRAM-based Analog Sigmoid Function for In-memory Computing. 319-323 - Vishesh Mishra
MEGA-MAC: A Merged Accumulation based Approximate MAC Unit for Error Resilient Applications. 325-328 - Prabha Sundaravadivel, Prosenjit Kumar Ghosh, Bikal Suwal:
IoT-enabled Soft Robotics for Electrical Engineers. 329-332 - Aibin Yan, Yu Chen, Shukai Song, Zijie Zhai, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications. 333-338 - Irith Pomeranz:
Compaction of Compressed Bounded Transparent-Scan Test Sets. 339-343 - Hari Addepalli, Irith Pomeranz:
Algorithms for the Selection of Applied Tests when a Stored Test Produces Many Applied Tests. 345-349 - Amin Shafiee
LoCI: An Analysis of the Impact of Optical Loss and Crosstalk Noise in Integrated Silicon-Photonic Neural Networks. 351-355 - Sina Shahhosseini, Yang Ni, Emad Kasaeyan Naeini, Mohsen Imani, Amir M. Rahmani, Nikil D. Dutt:
Flexible and Personalized Learning for Wearable Health Applications using HyperDimensional Computing. 357-360 - Jingwei Zhu, Lei Wang, Xun Xiao, Zhijie Yang, Ziyang Kang, Shiming Li, LingHui Peng:
An Event Based Gesture Recognition System Using a Liquid State Machine Accelerator. 361-365 - Febin Sunny, Mahdi Nikdast, Sudeep Pasricha:
A Silicon Photonic Accelerator for Convolutional Neural Networks with Heterogeneous Quantization. 367-371 - Lingyi Huang, Xiao Zang, Yu Gong, Chunhua Deng, Jingang Yi, Bo Yuan:
IMG-SMP: Algorithm and Hardware Co-Design for Real-time Energy-efficient Neural Motion Planning. 373-377 - Samuel J. Engers, Cheng Chu, Dawen Xu, Ying Wang, Fan Chen:
MOCCA: A Process Variation Tolerant Systolic DNN Accelerator using CNFETs in Monolithic 3D. 379-382 - Adam Z. Foshie, Charles Rizzo
Benchmark Comparisons of Spike-based Reconfigurable Neuroprocessor Architectures for Control Applications. 383-386 - Long Tan, Mingyu Yan, Xiaochun Ye, Dongrui Fan
HetGraph: A High Performance CPU-CGRA Architecture for Matrix-based Graph Analytics. 387-391 - Arijit Nath, Hemangee K. Kapoor:
CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main Memories. 393-396 - Chien-Fu Chen, Mikko H. Lipasti:
PrGEMM: A Parallel Reduction SpGEMM Accelerator. 397-401
Keynote III: Sanu Mathew
- Sanu K. Mathew:
Attack-Resistant Circuit Technologies for sub-5nm Secure Computing Platforms. 403
Session 5A: Hardware Security
- Kris Gaj:
Session details: Session 5A: Hardware Security. - Michael Cho, Keewoo Lee, Sunwoong Kim
HELPSE: Homomorphic Encryption-based Lightweight Password Strength Estimation in a Virtual Keyboard System. 405-410 - Ruchika Gupta, Vedika J. Kulkarni, John Jose, Sukumar Nandi:
Securing On-chip Interconnect against Delay Trojan using Dynamic Adaptive Caging. 411-416 - Xingyu Meng, Mahmudul Hasan, Kanad Basu, Tamzidul Hoque:
A Semi-formal Information Flow Validation for Analyzing Secret Asset Propagation in COTS IC Integrated Systems. 417-422
Session 5B: VLSI Design + VLSI Circuits and Power Aware Design 2
- Swaroop Ghosh:
Session details: Session 5B: VLSI Design + VLSI Circuits and Power Aware Design 2. - Lingfeng Chen, Tian Xia, Wenzhe Zhao, Pengju Ren:
MI2D: Accelerating Matrix Inversion with 2-Dimensional Tile Manipulations. 423-429 - Prashanth H. C.
Design and Evaluation of In-Exact Compressor based Approximate Multipliers. 431-436 - Omkar G. Ratnaparkhi, Madhav Rao:
LEAD: Logarithmic Exponent Approximate Divider For Image Quantization Application. 437-442
Session 6A: Special Session -1: Machine Learning and Hardware Attacks
- Qiaoyan Yu:
Session details: Session 6A: Special Session -1: Machine Learning and Hardware Attacks. - Yadi Zhong, Ujjwal Guin:
Fault-Injection Based Chosen-Plaintext Attacks on Multicycle AES Implementations. 443-448 - Hassan Salmani:
The Improved COTD Technique for Hardware Trojan Detection in Gate-level Netlist. 449-454 - Ashley Calhoun, Erick Ortega, Ferhat Yaman, Anuj Dubey, Aydin Aysu:
Hands-On Teaching of Hardware Security for Machine Learning. 455-461 - Satwik Kundu, Swaroop Ghosh:
Security Aspects of Quantum Machine Learning: Opportunities, Threats and Defenses. 463-468
Session 6B: Special Session - 2: Application-oriented Hardware Security Challenges and Solutions
- Hassan Salmani:
Session details: Session 6B: Special Session - 2: Application-oriented Hardware Security Challenges and Solutions. - Mohammad Mezanur Rahman Monjur, Joshua Calzadillas, Mashrafi Alam Kajol
Hardware Security in Advanced Manufacturing. 469-474 - Srivalli Boddupalli, Richard Owoputi
Resiliency in Connected Vehicle Applications: Challenges and Approaches for Security Validation. 475-480 - Weimin Fu, Honggang Yu, Orlando Arias, Kaichen Yang, Yier Jin, Tuba Yavuz, Xiaolong Guo:
Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC Platforms. 481-486 - Xiang Zhang, Ziyue Zhang, Ruyi Ding, Cheng Gongye, Aidong Adam Ding, Yunsi Fei:
Ran$Net: An Anti-Ransomware Methodology based on Cache Monitoring and Deep Learning. 487-492
Session 7A: Special Session - 3: Machine Learning-Aided Computer-Aided Design
- Sai Manoj Pudukotai Dinakarrao:
Session details: Session 7A: Special Session - 3: Machine Learning-Aided Computer-Aided Design. - Tanmoy Chowdhury, Ashkan Vakil, Banafsheh Saber Latibari, Sayed Aresh Beheshti-Shirazi, Ali Mirzaeian, Xiaojie Guo, Sai Manoj P. D., Houman Homayoun, Ioannis Savidis, Liang Zhao, Avesta Sasan:
RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis. 493-500 - Sreenitha Kasarapu, Sanket Shukla, Rakibul Hassan, Avesta Sasan, Houman Homayoun, Sai Manoj P. D.:
CAD-FSL: Code-Aware Data Generation based Few-Shot Learning for Efficient Malware Detection. 507-512 - Kevin Immanuel Gubbi, Sayed Aresh Beheshti-Shirazi, Tyler David Sheaves
Survey of Machine Learning for Electronic Design Automation. 513-518
Session 7B: Microelectronic Systems Education
- Brian J. Skromme:
Session details: Session 7B: Microelectronic Systems Education. - Sudeep Pasricha:
Embedded Systems Education in the 2020s: Challenges, Reflections, and Future Directions. 519-524 - Alec Vercruysse, M. Weston Miller, Joshua Brake
A Tutorial-style Single-cycle Fast Fourier Transform Processor. 525-530 - Abubakr Abdulgadir, Jens-Peter Kaps
Enhancing Information Security Courses With a Remotely Accessible Side-Channel Analysis Setup. 531-536 - Jennifer Hasler:
A Senior-Level Analog IC Design Course built on Open-Source Technologies. 537-542
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