default search action
19th ASYNC 2013: Santa Monica, CA, USA
- 19th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2013, Santa Monica, CA, USA, May 19-22, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-5956-6
- Vivek De:
Keynote: Variation-tolerant adaptive and resilient designs in nanoscale CMOS. - Jian Liu, Steven M. Nowick, Mingoo Seok:
Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages. 1-7 - Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems. 8-15 - Reza Ramezani, Alex Yakovlev
:
Capacitor Discharging Through Asynchronous Circuit Switching. 16-22 - Jakob Lechner, Varadan Savulimedu Veeravalli:
Modular Redundancy in a GALS System Using Asynchronous Recovery Links. 23-30 - Syed Rameez Naqvi, Andreas Steininger
An SET Tolerant Tree Arbiter Cell. 31-39 - Jonathan Tse, Andrew Lines:
NanoMesh: An Asynchronous Kilo-Core System-on-Chip. 40-49 - Bo Marr, Julia Karl, Lloyd Lewins, Ken Prager, Dan Thompson:
An Asynchronous Dataflow Signal Processing Architecture to Minimize Energy per Op. 50-57 - Robert Karmazin, Carlos Tadeo Ortega Otero, Rajit Manohar:
cellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells. 58-66 - Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin:
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. 67-74 - Mehrdad Najibi, Peter A. Beerel:
Deriving Performance Bounds for Conditional Asynchronous Circuits Using Linear Programing. 75-82 - Xin Fan, Oliver Schrape, Miroslav Marinkovic, Peter Dahnert, Milos Krstic
GALS Design for Spectral Peak Attenuation of Switching Current. 83-90 - Suwen Yang, Frankie Y. Liu:
Distributed Phase Correction Technique. 91-98 - Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet:
A Self-Timed Ring Based True Random Number Generator. 99-106 - Shomit Das, Vikas S. Vij, Kenneth S. Stevens:
SAS: Source Asynchronous Signaling Protocol for Asynchronous Handshake Communication Free from Wire Delay Overhead. 107-114 - Robert Najvirt, Syed Rameez Naqvi, Andreas Steininger
Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. 115-123 - Jonathan Tse, Benjamin Hill, Rajit Manohar:
A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. 124-133 - Fu-Chiung Cheng, Chi Chen:
Can QDI Combinational Circuits be Implemented without C-elements? 134-141 - Jérémie Hamon, Edith Beigné
Automatic Leakage Control for Wide Range Performance QDI Asynchronous Circuits in FD-SOI Technology. 142-149 - Stephen Longfield Jr., Rajit Manohar:
Inverting Martin Synthesis for Verification. 150-157 - Salomon Beer, Jerome Cox, Tom Chaney, David M. Zar:
MTBF Bounds for Multistage Synchronizers. 158-165 - Salomon Beer, Ran Ginosar, Rostislav (Reuven) Dobkin, Yoav Weizman:
MTBF Estimation in Coherent Clock Domains. 166-173 - Thomas Polzer, Andreas Steininger
An Approach for Efficient Metastability Characterization of FPGAs through the Designer. 174-182 - Freek Verbeek, Sebastiaan J. C. Joosten, Julien Schmaltz:
Formal Deadlock Verification for Click Circuits. 183-190 - Matthias Függer, Thomas Nowak
Unfaithful Glitch Propagation in Existing Binary Circuit Models. 191-199
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-19 22:02 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: