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"Design and Synthesis of Pareto Buffers Offering Large Range Runtime ..."

Hua Wang et al. (2009)

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DOI: 10.1109/TVLSI.2008.2003169

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/WangMDC09
Hua Wang, Miguel Miranda, Wim Dehaene, Francky Catthoor:
Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 117-127 (2009)

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