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"A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and ..."

Ik Joon Chang et al. (2009)

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DOI: 10.1109/JSSC.2008.2011972

access: closed

type: Journal Article

metadata version: 2020-08-30

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Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy:
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS. IEEE J. Solid State Circuits 44(2): 650-658 (2009)

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