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"A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer ..."
Xubin Chen et al. (2019)
- Xubin Chen, Xuan Li, Yupeng Shen, Jiarui Liu, Hua Chen:
A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS. IEICE Electron. Express 16(11): 20190197 (2019)
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