default search action

combined dblp search
author search
venue search
publication search

ask others

"4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor."

Penny Li et al. (2015)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2015.7062931

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/LiSKSKCDMZLLPSH15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/LiSKSKCDMZLLPSH15
Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister:
4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. ISSCC 2015: 1-3

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.