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"Timing-Abstract Circuit Design in Transaction-Level Verilog."

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Steven F. Hoover (2017)

Dagstuhl

Trier

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DOI: 10.1109/ICCD.2017.91

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Steven F. Hoover:
Timing-Abstract Circuit Design in Transaction-Level Verilog. ICCD 2017: 525-532

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last updated on 2023-03-23 23:59 CET by the dblp team

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