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Mark Vesterbacka
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- affiliation: Linköping University, Sweden
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2010 – 2019
- 2018
- [c36]Mark Vesterbacka, Vishnu Unnikrishnan
:
Ring Counters as Phase Accumulator in VCO-Based ADCs. ICECS 2018: 109-112 - 2017
- [j6]Vishnu Unnikrishnan
Mitigation of Sampling Errors in VCO-Based ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1730-1739 (2017) - [c35]Shahzad Asif, Mark Vesterbacka:
An RNS based modular multiplier with reduced complexity. NORCAS 2017: 1-4 - 2016
- [c34]Vishnu Unnikrishnan
VCO-based ADCs for IoT applications. ISIC 2016: 1-4 - [c33]Vishnu Unnikrishnan
Mixed-Signal Design Using Digital CAD. ISVLSI 2016: 6-11 - [c32]Vishnu Unnikrishnan
Linearization of VCO-based ADCs using asynchronous sigma-delta modulation. MWSCAS 2016: 1-4 - [c31]Vishnu Unnikrishnan
Design of a VCO-based ADC in 28 nm CMOS. NORCAS 2016: 1-4 - 2015
- [c30]Muhammad Touqir Pasha, Niklas U. Andersson, Mark Vesterbacka:
Power-efficient time-to-digital converter for all-digital frequency locked loops. ECCTD 2015: 1-4 - [c29]Vishnu Unnikrishnan
Linearization of synthesizable VCO-based ADCs using delta modulation. ECCTD 2015: 1-4 - [c28]Vishnu Unnikrishnan
A fully synthesized all-digital VCO-based analog-to-digital converter. NORCAS 2015: 1-4 - [c27]Vishnu Unnikrishnan
A NAND gate based standard cell VCO for use in synthesizable ADCs. NORCAS 2015: 1-4 - 2014
- [j5]Niklas U. Andersson, Mark Vesterbacka:
A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture. IEEE Trans. Circuits Syst. II Express Briefs 61-II(10): 773-777 (2014) - [j4]Vishnu Unnikrishnan
Time-Mode Analog-to-Digital Conversion Using Standard Cells. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3348-3357 (2014) - [c26]Muhammad Touqir Pasha, Mark Vesterbacka:
A modified switching scheme for multiplexer based thermometer-to-binary encoders. NORCHIP 2014: 1-4 - 2012
- [j3]Shahzad Asif, Mark Vesterbacka:
Performance analysis of radix-4 adders. Integr. 45(2): 111-120 (2012) - 2011
- [c25]Muhammad Touqir Pasha, Mark Vesterbacka:
Frequency control schemes for single-ended ring oscillators. ECCTD 2011: 361-364 - 2010
- [j2]S. M. Yasser Sherazi, Shahzad Asif, Erik Backenius, Mark Vesterbacka:
Reduction of Substrate Noise in Sub Clock Frequency Range. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(6): 1287-1297 (2010) - [c24]Armin Jalili, Sayed Masoud Sayedi, J. Jacob Wikner
Calibration of high-resolution flash ADCS based on histogram test methods. ICECS 2010: 114-117
2000 – 2009
- 2007
- [c23]Erik Backenius, Mark Vesterbacka, V. B. Settu:
Reduction of simultaneous switching noise in analog signal band. ECCTD 2007: 148-151 - [c22]Erik Säll, Mark Vesterbacka:
Thermometer-to-binary decoders for flash analog-to-digital converters. ECCTD 2007: 240-243 - 2006
- [c21]Erik Backenius, Mark Vesterbacka:
Effect of Simultaneous Switching Noise on an Analog Filter. ICECS 2006: 898-901 - [c20]Magnus Karlsson, Mark Vesterbacka:
Digit-serial/parallel multipliers with improved throughput and latency. ISCAS 2006 - 2005
- [j1]K. Ola Andersson, Mark Vesterbacka:
Modeling of glitches due to rise/fall asymmetry in current-steering digital-to-analog converters. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(11): 2265-2275 (2005) - [c19]K. Ola Andersson, Mark Vesterbacka:
A yield-enhancement strategy for binary-weighted DACs. ECCTD 2005: 55-58 - [c18]Erik Säll, Mark Vesterbacka:
6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applications. ECCTD 2005: 127-130 - [c17]Krister Landernäs, Johnny Holmberg, Mark Vesterbacka:
Glitch reduction in digit-serial recursive filters using retiming. ICECS 2005: 1-4 - 2004
- [c16]Erik Säll, Mark Vesterbacka, K. Ola Andersson:
A study of digital decoders in flash analog-to-digital converters. ISCAS (1) 2004: 129-132 - [c15]Krister Landernäs, Johnny Holmberg, Mark Vesterbacka:
A high-speed low-latency digit-serial hybrid adder. ISCAS (3) 2004: 217-220 - [c14]Magnus Karlsson, Mark Vesterbacka, Wlodek Kulesza:
A method for increasing the throughput of fixed coefficient digit-serial/parallel multipliers. ISCAS (2) 2004: 425-428 - [c13]K. Ola Andersson, Mark Vesterbacka:
A Parameterized Cell-Based Design Approach for Digital-to-Analog Converters. IWSOC 2004: 225-228 - [c12]Erik Säll, Mark Vesterbacka:
Design of a Comparator in CMOS SOI. IWSOC 2004: 229-232 - 2002
- [c11]K. Ola Andersson, Niklas U. Andersson, Mark Vesterbacka, J. Jacob Wikner:
A differential DAC architecture with variable common-mode level. ISCAS (1) 2002: 113-116 - [c10]Robert Hägglund, Per Löwenborg, Mark Vesterbacka:
A polynomial-based division algorithm. ISCAS (3) 2002: 571-574 - 2001
- [c9]Mark Vesterbacka, J. Jacob Wikner
Design of encoders for linear-coded D/A converters. ISCAS (1) 2001: 524-527 - 2000
- [c8]Mark Vesterbacka, Mikael Rudberg, J. Jacob Wikner
Dynamic element matching in D/A converters with restricted scrambling. ICECS 2000: 36-39 - [c7]Mark Vesterbacka:
A static CMOS master-slave flip-flop experiment. ICECS 2000: 870-873 - [c6]Mikael Karlsson Rudberg, Mark Vesterbacka, Niklas U. Andersson, J. Jacob Wikner
Glitch minimization and dynamic element matching in D/A converters. ICECS 2000: 899-902
1990 – 1999
- 1999
- [c5]Mark Vesterbacka:
A robust differential scan flip-flop. ISCAS (1) 1999: 334-337 - 1996
- [c4]Mark Vesterbacka, Kent Palmkvist, Lars Wanhammar:
Sign-extension and quantization in bit-serial digital filters. ICECS 1996: 394-397 - [c3]Kent Palmkvist, Mark Vesterbacka, Lars Wanhammar:
Implementation of static DSP algorithms using multiplexed PE: s. ICECS 1996: 824-827 - 1994
- [c2]Peter Nilsson, Mats Torkelson, Kent Palmkvist, Mark Vesterbacka, Lars Wanhammar:
A Bit-Serial CMOS Digital IF-Filter for Mobile Radio Using an On-Chip Clock. Mobile Communications 1994: 510-521 - [c1]Mark Vesterbacka, Kent Palmkvist, Peter Sandberg, Lars Wanhammar:
Implementation of Fast Bit-Serial Lattice Wave Digital Filters. ISCAS 1994: 113-116
Coauthor Index
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