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Harish Patil
Person information
- affiliation: University of Wisconsin-Madison, Madison, USA
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2020 – today
- 2022
- [c17]Alen Sabu
, Harish Patil, Wim Heirman, Trevor E. Carlson:
LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications. HPCA 2022: 604-618 - 2021
- [c16]Harish Patil, Alexander Isaev, Wim Heirman, Alen Sabu
ELFies: Executable Region Checkpoints for Performance Analysis and Simulation. CGO 2021: 126-136
2010 – 2019
- 2015
- [c15]Melanie Kambadur, Sunpyo Hong, Juan Cabral, Harish Patil, Chi-Keung Luk, Sohaib Sajid, Martha A. Kim
Fast Computational GPU Design with GT-Pin. IISWC 2015: 76-86 - [c14]Charles Yount, Harish Patil, Mohammad S. Islam, Aditya Srikanth:
Graph-matching-based simulation-region selection for multiple binaries. ISPASS 2015: 52-61 - 2014
- [c13]Yan Wang, Harish Patil, Cristiano Pereira, Gregory Lueck, Rajiv Gupta, Iulian Neamtiu:
DrDebug: Deterministic Replay based Cyclic Debugging with Dynamic Slicing. CGO 2014: 98 - 2012
- [c12]Gregory Lueck, Harish Patil, Cristiano Pereira:
PinADX: an interface for customizable debugging with dynamic instrumentation. CGO 2012: 114-123 - 2010
- [j4]Moshe Bach, Mark Charney, Robert Cohn, Elena Demikhovsky, Tevi Devor, Kim M. Hazelwood, Aamer Jaleel, Chi-Keung Luk, Gail Lyons, Harish Patil, Ady Tal:
Analyzing Parallel Programs with Pin. Computer 43(3): 34-41 (2010) - [c11]Harish Patil, Cristiano Pereira, Mack Stallcup, Gregory Lueck, James Cownie:
PinPlay: a framework for deterministic replay and reproducible analysis of parallel programs. CGO 2010: 2-11
2000 – 2009
- 2008
- [c10]Cristiano Pereira, Harish Patil, Brad Calder:
Reproducible simulation of multi-threaded workloads for architecture design exploration. IISWC 2008: 173-182 - 2007
- [c9]Erez Perelman, Jeremy Lau, Harish Patil, Aamer Jaleel, Greg Hamerly
Cross Binary Simulation Points. ISPASS 2007: 179-189 - 2006
- [c8]Satish Narayanasamy
Automatic logging of operating system effects to guide application-level architecture simulation. SIGMETRICS/Performance 2006: 216-227 - 2005
- [c7]Chi-Keung Luk, Robert S. Cohn
Pin: building customized program analysis tools with dynamic instrumentation. PLDI 2005: 190-200 - 2004
- [c6]Chi-Keung Luk, Robert Muth, Harish Patil, Robert S. Cohn, P. Geoffrey Lowney:
Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture. CGO 2004: 15-26 - [c5]Harish Patil, Robert S. Cohn
Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation. MICRO 2004: 81-92 - 2002
- [j3]Joel S. Emer, Pritpal S. Ahuja, Eric Borch, Artur Klauser
Asim: A Performance Model Framework. Computer 35(2): 68-76 (2002) - [c4]Chi-Keung Luk, Robert Muth, Harish Patil, Richard Weiss, P. Geoffrey Lowney, Robert S. Cohn:
Profile-guided post-link stride prefetching. ICS 2002: 167-178 - 2000
- [c3]Harish Patil, Joel S. Emer:
Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing. HPCA 2000: 251-262
1990 – 1999
- 1999
- [c2]Le-Chun Wu, Rajiv Mirani, Harish Patil, Bruce Olsen, Wen-mei W. Hwu:
A New Framework for Debugging Globally Optimized Code. PLDI 1999: 181-191 - 1997
- [j2]Harish Patil, Charles N. Fischer:
Low-Cost, Concurrent Checking of Pointer and Array Accesses in C Programs. Softw. Pract. Exp. 27(1): 87-110 (1997) - 1996
- [b1]Harish Patil:
Efficient program monitoring techniques. University of Wisconsin-Madison, WI, USA, Technical Report / University of Wisconsin, Madison / Computer Sciences Department 1320, 1996, pp. I-VIII, 1-66 - 1995
- [c1]Harish Patil, Charles N. Fischer:
Efficient Run-time Monitoring Using Shadow Processing. AADEBUG 1995: 119-132 - 1993
- [j1]Dhananjay M. Dhamdhere, Harish Patil:
An Elimination Algorithm for Bidirectional Data Flow Problems Using Edge Placement. ACM Trans. Program. Lang. Syst. 15(2): 312-336 (1993)
Coauthor Index
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