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Katsuhiko Degawa
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2010 – 2019
- 2015
- [c11]Takahiro J. Yamaguchi, Katsuhiko Degawa, Masayuki Kawabata, Masahiro Ishida, Koichiro Uekusa, Mani Soma:
A new method for measuring alias-free aperture jitter in an ADC output. ITC 2015: 1-6 - 2011
- [c10]Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada:
An equivalent-time and clocked approach for continuous-time quantization. ISCAS 2011: 2529-2532 - [c9]Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu:
Application of a continuous-time level crossing quantization method for timing noise measurements. ITC 2011: 1-10
2000 – 2009
- 2009
- [j5]Naofumi Homma, Yuki Watanabe, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. J. Multiple Valued Log. Soft Comput. 15(4): 329-340 (2009) - [c8]Albert Tumewu, Kazuyuki Miyazawa, Takafumi Aoki, Takahiro J. Yamaguchi, Katsuhiko Degawa, Takayuki Akita:
Phase-based alignment of two signals having partially overlapped spectra. ICASSP 2009: 3337-3340 - 2008
- [c7]Yuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. ISMVL 2008: 112-117 - 2007
- [j4]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi:
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors. J. Multiple Valued Log. Soft Comput. 13(3): 249-266 (2007) - [j3]Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams. J. Multiple Valued Log. Soft Comput. 13(4-6): 487-502 (2007) - [c6]Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. ISMVL 2007: 31 - 2006
- [c5]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa
, Katsuhiko Nishiguchi, Yasuo Takahashi:
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. ISMVL 2006: 19 - 2005
- [j2]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects. J. Multiple Valued Log. Soft Comput. 11(5-6): 545-565 (2005) - [c4]Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi:
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. ISMVL 2005: 32-38 - 2004
- [c3]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. ISMVL 2004: 262-268 - [c2]Hiroshi Inokawa
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. ISMVL 2004: 269-274 - 2003
- [j1]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(8): 2001-2010 (2003) - [c1]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic. ISMVL 2003: 213-220
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