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Sriram Vajapeyam
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2010 – 2019
- 2014
- [i1]Sriram Vajapeyam:
Understanding Shannon's Entropy metric for Information. CoRR abs/1405.2061 (2014)
2000 – 2009
- 2002
- [j4]Siddhartha V. Tambat, Sriram Vajapeyam:
Page-Level Behavior of Cache Contention. IEEE Comput. Archit. Lett. 1 (2002) - 2001
- [j3]Sriram Vajapeyam, Mateo Valero
:
Early 21st Century Processors - Guest Editors' Introduction. Computer 34(4): 47-50 (2001) - [e2]Burkhard Monien, Viktor K. Prasanna, Sriram Vajapeyam:
High Performance Computing - HiPC 2001, 8th International Conference, Hyderabad, India, December, 17-20, 2001, Proceedings. Lecture Notes in Computer Science 2228, Springer 2001, ISBN 3-540-43009-1 [contents] - 2000
- [c12]Siddhartha V. Tambat, Sriram Vajapeyam:
Non-Strict Cache Coherence: Exploiting Data-Race Tolerance in Emerging Applications. ICPP 2000: 87-94 - [e1]Mateo Valero, Viktor K. Prasanna, Sriram Vajapeyam:
High Performance Computing - HiPC 2000, 7th International Conference, Bangalore, India, December 17-20, 2000, Proceedings. Lecture Notes in Computer Science 1970, Springer 2000, ISBN 3-540-41429-0 [contents]
1990 – 1999
- 1999
- [c11]Sriram Vajapeyam:
Whither Indian Computer Science R & D? HiPC 1999: 175 - [c10]Sriram Vajapeyam, P. J. Joseph, Tulika Mitra:
Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs. ISCA 1999: 16-27 - 1998
- [c9]Sridhar Gopal, Sriram Vajapeyam:
Load Balancing in a Heterogeneous Computing Environment. HICSS (7) 1998: 796- - [c8]Gurindar S. Sohi, Sriram Vajapeyam:
Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. 25 Years ISCA: Retrospectives and Reprints 1998: 329-336 - 1997
- [j2]James E. Smith, Sriram Vajapeyam:
Trace Processors: Moving to Fourth-Generation Microarchitectures. Computer 30(9): 68-74 (1997) - [c7]Sriram Vajapeyam, Tulika Mitra:
Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences. ISCA 1997: 1-12 - 1996
- [c6]P. J. Joseph, Sriram Vajapeyam:
Program-level control of network delay for parallel asynchronous iterative applications. HiPC 1996: 88-93 - 1993
- [j1]Sriram Vajapeyam, Wei-Chung Hsu
Toward Effective Scalar Hardware for Highly Vectorizable Applications. J. Parallel Distributed Comput. 19(3): 147-162 (1993) - 1992
- [c5]Sriram Vajapeyam, Wei-Chung Hsu:
On the instruction-level characteristics of scalar code in highly-vectorized scientific applications. MICRO 1992: 20-28 - 1991
- [c4]Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu:
An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks. ISCA 1991: 170-179 - 1990
- [c3]Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu:
Exploitation of operation-level parallelism in a processor of the CRAY X-MP. ICCD 1990: 20-23
1980 – 1989
- 1989
- [c2]Gurindar S. Sohi, Sriram Vajapeyam:
Tradeoffs in Instruction Format Design for Horizontal Architectures. ASPLOS 1989: 15-25 - 1987
- [c1]Gurindar S. Sohi, Sriram Vajapeyam:
Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. ISCA 1987: 27-34
Coauthor Index
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