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Mark Chan
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2010 – 2019
- 2014
- [j2]Paul Atchley
, Mark Chan, Sabrina Gregersen:
A Strategically Timed Verbal Task Improves Performance and Neurophysiological Alertness During Fatiguing Drives. Hum. Factors 56(3): 453-462 (2014) - 2013
- [c7]David M. Lewis, David Cashman, Mark Chan, Jeffrey Chromczak, Gary Lai, Andy Lee, Tim Vanderhoek, Haiming Yu:
Architectural enhancements in Stratix V™. FPGA 2013: 147-156 - 2011
- [j1]Paul Atchley
Potential Benefits and Costs of Concurrent Task Engagement to Maintain Vigilance: A Driving Simulator Investigation. Hum. Factors 53(1): 3-12 (2011)
2000 – 2009
- 2009
- [c6]Yanzhong Xu, Lin-Shih Liu, Mark Chan, Jeff Watt:
Process variation impact on FPGA configuration memory. ISQED 2009: 613-616 - 2005
- [c5]Mark Chan, Patrice Delmas, Georgy L. Gimel'farb, Philippe Leclercq:
Comparative Study of 3D Face Acquisition Techniques. CAIP 2005: 740-747 - 2004
- [c4]Mark Chan, Chia-Yen Chen, Gareth Barton, Patrice Delmas, Georgy L. Gimel'farb, Philippe Leclercq, Thomas Fischer:
Evaluation of 3D face analysis and synthesis techniques. ICME 2004: 1203-1206 - [c3]Mark Chan, Patrice Delmas, Georgy L. Gimel'farb, Chia-Yen Chen, Philippe Leclercq:
Study and Comparison of 3D Face Generation. PRICAI 2004: 987-988 - 2003
- [c2]Paul Leventis, Mark Chan, Michael Chan, David M. Lewis, Behzad Nouban, Giles Powell, Brad Vest, Myron Wong, Renxin Xia, John Costello:
Cyclone ™: a low-cost, high-performance FPGA. CICC 2003: 49-52
1990 – 1999
- 1999
- [c1]Brad Vest, Gwen Liang, Mark Chan, Eric Chun, Mark Fiester, Weiying Ding, Edmond Lau, Guu Lin, Behzad Nouban, Dirk Reese, Mian Smith, Nghia Tran, Stephanie Wong, Michael Woo, Myron Wong, John Costello:
A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming. CICC 1999: 187-190
Coauthor Index
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