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Xiangyu Zhang 0002
Person information
- affiliation: ShanghaiTech University, School of Information Science and Technology, China
- affiliation (PhD 2019): Hiroshima University, Graduate School of Engineering, Japan
Other persons with the same name
- Xiangyu Zhang — disambiguation page
- Xiangyu Zhang 0001
— Purdue University, West Lafayette, IN, USA (and 1 more)
- Xiangyu Zhang 0003
- Xiangyu Zhang 0004
- Xiangyu Zhang 0005
- Xiangyu Zhang 0007
- Xiangyu Zhang 0008
- Xiangyu Zhang 0009 — Northwestern Polytechnical University, China
- Xiangyu Zhang 0010
- Xiangyu Zhang 0011
- Xiangyu Zhang 0012 — Cornell University, Department of Operations Research and Information Engineering, Ithaca, NY, USA
- Xiangyu Zhang 0013
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2020 – today
- 2024
- [j12]Ling Zhang
RAW Images-Based Motion-Assisted Object Detection Accelerator Using Deformable Parts Models Features on 1080p Videos. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 5054-5066 (2024) - [j11]Kangjie Long
FPGA Accelerator for Human Activity Recognition Based on Radar. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1441-1445 (2024) - [c13]Hongyu Wang, Xiangyu Zhang, Xin Lou:
A Multi-scale Block PatchMatch-based Unified Algorithm for Efficient 6-D Vision Processing. ISCAS 2024: 1-5 - 2023
- [c12]Mengchuan Dong, Wei Zhou, Cong Pang, Xiangyu Zhang, Xin Lou:
Image Frequency Separation Residual Network for End-to-end RAW to RGB Mapping. AICAS 2023: 1-5 - [c11]Haoyan Li, Wei Zhou, Xiangyu Zhang, Xin Lou:
An Efficient Frequency Domain Vision Pipeline From RAW Images to Backend Tasks. ISCAS 2023: 1-5 - 2022
- [j10]Xiangyu Zhang
A Raw Image-Based End-to-End Object Detection Accelerator Using HOG Features. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 322-333 (2022) - [j9]Hongyu Wang
A Block PatchMatch-Based Energy-Resource Efficient Stereo Matching Processor on FPGA. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2893-2905 (2022) - [c10]Kangjie Long, Chaolin Rao, Xiangyu Zhang, Wen Bin Ye, Xin Lou:
FPGA Accelerator for Radar-Based Human Activity Recognition. AICAS 2022: 391-394 - [c9]Hongyu Wang
A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA. CICC 2022: 1-2 - [c8]Ling Zhang, Wei Zhou, Xiangyu Zhang, Xin Lou:
An End-to-end Computer Vision System Architecture. ISCAS 2022: 2338-2342 - 2021
- [c7]Shengyu Gao
Motion Assisted Video-based Stereo Matching. APCCAS 2021: 57-60 - [c6]Wangchao Liu, Teng Wang, Yang Wang, Xiangyu Zhang, Xin Lou:
Stereo Point Cloud Refinement for 3D Object Detection. APCCAS 2021: 61-64 - [c5]Jianhua Geng, Sifan Wang, Juan Li, Jingwei Li, Xiangyu Zhang, Xin Lou:
Robust Multi-Source Direction of Arrival Estimation Using a Single Acoustic Vector Sensor. APCCAS 2021: 161-164 - [c4]Xiangyu Zhang, Wenyan Su, Juan Li, Jingwei Li, Xin Lou:
Spatial Non-Maximum Suppression for Object Detection using Correlation and Dynamic Thresholds. ISOCC 2021: 264-265
2010 – 2019
- 2019
- [j8]Aiwen Luo
A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier. IEEE Access 7: 14472-14487 (2019) - [j7]Jungang Guan, Fengwei An
Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm. IEICE Trans. Inf. Syst. 102-D(6): 1171-1182 (2019) - 2018
- [j6]Xiangyu Zhang
A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3312-3325 (2018) - [j5]Fengwei An
A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space. IEEE Trans. Circuits Syst. Video Technol. 28(10): 3086-3098 (2018) - [j4]Aiwen Luo
Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 431-444 (2018) - 2017
- [j3]Zunkai Huang
A Vector-Quantization Compression Circuit With On-Chip Learning Ability for High-Speed Image Sensor. IEEE Access 5: 22132-22143 (2017) - [j2]Jungang Guan, Fengwei An
Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures. Sensors 17(2): 270 (2017) - [c3]Fengwei An
Object-recognition VLSI for pedestrian detection in automotive applications. ASICON 2017: 651-653 - 2016
- [j1]Fengwei An
A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration. IEEE Trans. Multi Scale Comput. Syst. 2(4): 234-241 (2016) - [c2]Yuki Fujita, Fengwei An
Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction. APCCAS 2016: 611-612 - [c1]Fengwei An
Dynamically reconfigurable system for LVQ-based on-chip learning and recognition. ISCAS 2016: 1338-1341
Coauthor Index
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