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Bruno da Silva 0001
Person information
- affiliation: Vrije Universiteit Brussel, Department of Engineering Technology / Department of Electronics and Informatics, Belgium
Other persons with the same name
- Bruno da Silva 0002
(aka: Bruno Carreiro da Silva, Bruno C. da Silva 0002) — California Polytechnic State University, San Luis Obispo, CA, USA (and 1 more)
- Bruno da Silva 0003 — University of Lyon, France (and 1 more)
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2020 – today
- 2024
- [j17]Joan Lambert Cause
Evaluating Vascular Depth-Dependent Changes in Multi-Wavelength PPG Signals Due to Contact Force. Sensors 24(9): 2692 (2024) - [j16]Laurent Segers
Trustworthy Environmental Monitoring Using Hardware-Assisted Security Mechanisms. Sensors 24(14): 4720 (2024) - [c23]An Braeken
Trusted Computing Architectures for IoT Devices. ARC 2024: 241-254 - 2023
- [j15]Joan Lambert Cause
Novel Multi-Parametric Sensor System for Comprehensive Multi-Wavelength Photoplethysmography Characterization. Sensors 23(14): 6628 (2023) - [j14]Vlad-Eusebiu Baciu
Anomaly Detection in Multi-Wavelength Photoplethysmography Using Lightweight Machine Learning Algorithms. Sensors 23(15): 6947 (2023) - [j13]Chao Chen
AutoMLP: A Framework for the Acceleration of Multi-Layer Perceptron Models on FPGAs for Real-Time Atrial Fibrillation Disease Detection. IEEE Trans. Biomed. Circuits Syst. 17(6): 1371-1386 (2023) - [j12]Chao Chen
Acceleration of Bucket-Assisted Fast Sample Entropy for Biomedical Signal Analysis. IEEE Trans. Instrum. Meas. 72: 1-11 (2023) - 2022
- [j11]Chao Chen
Evaluation of Fast Sample Entropy Algorithms on FPGAs: From Performance to Energy Efficiency. Entropy 24(9): 1177 (2022) - [j10]Ángel Solé Morillo
PPG EduKit: An Adjustable Photoplethysmography Evaluation System for Educational Activities. Sensors 22(4): 1389 (2022) - [c22]Chao Chen
Acceleration of Fast Sample Entropy Towards Biomedical Applications on FPGAs. FPT 2022: 1-4 - [c21]Ángel Solé Morillo
Effect of the Transimpedance Amplifier Topology on the Photoplethysmography Signal. IECON 2022: 1-7 - [c20]Workineh Tesema
Power Saving Techniques for Wearable Devices in Medical Applications. IECON 2022: 1-8 - [c19]Jurgen Vandendriessche
Frequency Evaluation of the Xilinx DPU Towards Energy Efficiency. IECON 2022: 1-6 - 2021
- [j9]Feras Almasri
XCycles Backprojection Acoustic Super-Resolution. Sensors 21(10): 3453 (2021) - [c18]Marcelo Brandalero, Mitko Veleski, Hector Gerardo Muñoz Hernandez, Muhammad Ali, Laurens Le Jeune, Toon Goedemé
AITIA: Embedded AI Techniques for Industrial Applications. FPL 2021: 374-375 - [i1]Feras Almasri, Jurgen Vandendriessche, Laurent Segers, Bruno da Silva, An Braeken, Kris Steenhaut, Abdellah Touhafi, Olivier Debeir:
XCycles Backprojection Acoustic Super-Resolution. CoRR abs/2105.09128 (2021) - 2020
- [c17]Marcelo Brandalero, Muhammad Ali, Laurens Le Jeune
AITIA: Embedded AI Techniques for Embedded Industrial Applications. COINS 2020: 1-7
2010 – 2019
- 2019
- [j8]Bruno da Silva
Design Exploration and Performance Strategies towards Power-Efficient FPGA-Based Architectures for Sound Source Localization. J. Sensors 2019: 5761235:1-5761235:27 (2019) - [j7]Laurent Segers
CABE: A Cloud-Based Acoustic Beamforming Emulator for FPGA-Based Sound Source Localization. Sensors 19(18): 3906 (2019) - [c16]Bruno da Silva
Probabilistic Performance Modelling when Using Partial Reconfiguration to Accelerate Streaming Applications with Non-deterministic Task Scheduling. ARC 2019: 81-95 - [c15]Bruno da Silva
Demonstration of a Multimode SoC FPGA-Based Acoustic Camera. FPL 2019: 419-420 - 2018
- [j6]Bruno da Silva
FPGA-Based Architectures for Acoustic Beamforming with Microphone Arrays: Trends, Challenges and Research Opportunities. Comput. 7(3): 41 (2018) - [j5]Bruno da Silva
Exploiting Partial Reconfiguration through PCIe for a Microphone Array Network Emulator. Int. J. Reconfigurable Comput. 2018 (2018) - [j4]Jan Lemeire
Efficiency analysis methodology of FPGAs based on lost frequencies, area and cycles. J. Parallel Distributed Comput. 113: 204-217 (2018) - [c14]Bruno da Silva
A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks. ARC 2018: 281-293 - [c13]Laurent Segers, Bruno da Silva
Cloud-Based Acoustic Beamforming Emulator for FPGA-Based Sound Source Localization. Cloudtech 2018: 1-6 - [c12]Bruno da Silva
Heterogeneous Cloud Computing: Design Methodology to Combine Hardware Accelerators. Cloudtech 2018: 1-8 - [c11]Bruno da Silva
A Multimode SoC FPGA-Based Acoustic Camera for Wireless Sensor Networks. ReCoSoC 2018: 1-8 - 2017
- [j3]Bruno da Silva
Design Considerations When Accelerating an FPGA-Based Digital Microphone Array for Sound-Source Localization. J. Sensors 2017: 6782176:1-6782176:20 (2017) - [c10]Bruno da Silva
A partial reconfiguration based microphone array network emulator. FPL 2017: 1-4 - [c9]Bruno da Silva
Demonstration of a partial reconfiguration based microphone array network emulator. FPL 2017: 1 - 2016
- [c8]Bruno da Silva
A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis. ARC 2016: 334-342 - [c7]Bruno da Silva
Runtime reconfigurable beamforming architecture for real-time sound-source localization. FPL 2016: 1-4 - [c6]Bruno da Silva
A runtime reconfigurable FPGA-based microphone array for sound source localization. FPL 2016: 1 - 2015
- [c5]Nele Mentens
DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications. ARC 2015: 513-518 - 2014
- [j2]Jelmer Tiete, Federico Domínguez
SoundCompass: A Distributed MEMS Microphone Array-Based Sensor for Sound Source Localization. Sensors 14(2): 1918-1949 (2014) - 2013
- [j1]Bruno da Silva
Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools. Int. J. Reconfigurable Comput. 2013: 428078:1-428078:10 (2013) - [c4]Bruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire:
Performance and toolchain of a combined GPU/FPGA desktop (abstract only). FPGA 2013: 274 - [c3]Bruno da Silva
Comparing and combining GPU and FPGA accelerators in an image processing context. FPL 2013: 1-4 - [c2]Bruno da Silva
Performance and Resource Modeling for FPGAs using High-Level Synthesis tools. PARCO 2013: 523-531 - 2012
- [c1]Bruno da Silva
Performance and Programming Environment of a Combined GPU/FPGA Desktop. High Performance Computing Workshop (2) 2012: 177-193
Coauthor Index
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last updated on 2024-10-07 21:12 CEST by the dblp team
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