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Shiro Kamohara
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2010 – 2019
- 2017
- [c9]Takumi Hasegawa, Yoshiki Yamamoto, Hideki Makiyama, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi:
SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive. ICICDT 2017: 1-4 - 2015
- [j5]Koichiro Ishibashi, Nobuyuki Sugii
, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. IEICE Trans. Electron. 98-C(7): 536-543 (2015) - [j4]Toshitsugu Sakamoto, Yukihide Tsuji
A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM. IEEE Micro 35(6): 13-23 (2015) - [c8]Toshitsugu Sakamoto, Yukihide Tsuji
0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM. COOL Chips 2015: 1-3 - [c7]Duc-Hung Le
Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process. ICICDT 2015: 1-4 - 2014
- [c6]Koichiro Ishibashi, Nobuyuki Sugii
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. COOL Chips 2014: 1-3 - [c5]Shiro Kamohara, Nobuyuki Sugii
A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode. Hot Chips Symposium 2014: 1 - 2011
- [j3]Chizu Matsumoto, Yuichi Hamamura, Yoshiyuki Tsunoda, Hiroshi Uozaki, Isao Miyazaki, Shiro Kamohara, Yoshiyuki Kaneko, Kenji Kanamitsu:
A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis. IEICE Trans. Electron. 94-C(3): 353-360 (2011)
2000 – 2009
- 2007
- [j2]Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago, Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya:
Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node. IEEE J. Solid State Circuits 42(6): 1362-1369 (2007) - 2005
- [j1]Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh:
A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. IEEE J. Solid State Circuits 40(4): 870-876 (2005) - 2004
- [c4]Kenichi Osada, Naoki Kitai, Shiro Kamohara, Takayuki Kawahara:
Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. CICC 2004: 357-360 - 2002
- [c3]Yuichi Hamamura, Kazunori Nemoto, Takaaki Kumazawa, Hisafumi Iwata, Kousuke Okuyama, Shiro Kamohara, Aritoshi Sugimoto:
Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure. DFT 2002: 305-313 - 2000
- [c2]Mikako Miyama, Shiro Kamohara:
Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters. ASP-DAC 2000: 371-374
1990 – 1999
- 1999
- [c1]Mikako Miyama, Shiro Kamohara, Mitsuru Hiraki, Kazunori Onozawa, Hisaaki Kunitomo:
Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent design. CICC 1999: 359-363
Coauthor Index
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