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José Luis Imaña
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2020 – today
- 2024
- [j22]Daniel C. Lawo
, Raphael Frantz, Abraham Cano Aguilera, X. Arnal I Clemente, M. P. Podles, José Luis Imaña
Falcon/Kyber and Dilithium/Kyber Network Stack on Nvidia's Data Processing Unit Platform. IEEE Access 12: 38048-38056 (2024) - [j21]Daniel C. Lawo
Wireless and Fiber-Based Post-Quantum-Cryptography-Secured IPsec Tunnel. Future Internet 16(8): 300 (2024) - [j20]José Luis Imaña
Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. IEEE Trans. Circuits Syst. II Express Briefs 71(8): 3915-3919 (2024) - [c10]Daniel C. Lawo, Michal Podles, Raphael Frantz, Abraham Cano Aguilera, Dimosthenis Iliadis-Apostolidis, Jeronimo Sanchez, Sokol Kosta
The zero-tax data center: a use case through quantum resilient communications. ICTON 2024: 1-4 - [c9]Abraham Cano Aguilera, Rana Abu Bakar, Faris Alhamed, Carlos Rubio Garcia, José Luis Imaña, Idelfonso Tafur Monroy, Filippo Cugini, J. J. Vegas Olmos:
First Line-rate End-to-End Post-Quantum Encrypted Optical Fiber Link Using Data Processing Units (DPUs). OFC 2024: 1-3 - 2023
- [j19]José Luis Imaña
Domain-oriented masked bit-parallel finite-field multiplier against side-channel attacks. Inf. Process. Lett. 182: 106395 (2023) - [j18]José Luis Imaña
Hardware architecture of Dillon's APN permutation for different primitive polynomials. Microprocess. Microsystems 103: 104945 (2023) - 2022
- [j17]José Luis Imaña
Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3297-3307 (2022) - [j16]Jiafeng Xie
Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography. IEEE Trans. Emerg. Top. Comput. 10(2): 1222-1228 (2022) - [c8]Tianyou Bao
Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography. CODES+ISSS 2022: 5-6 - [c7]José Luis Imaña
Decomposition of Dillon's APN Permutation with Efficient Hardware Implementation. WAIFI 2022: 250-268 - 2021
- [j15]José Luis Imaña
Optimized reversible quantum circuits for ${\mathbb {F}}_{2^8}$ multiplication. Quantum Inf. Process. 20(1): 27 (2021) - [j14]José Luis Imaña
LFSR-Based Bit-Serial GF(2m) Multipliers Using Irreducible Trinomials. IEEE Trans. Computers 70(1): 156-162 (2021) - [j13]José Luis Imaña
Low-Delay FPGA-Based Implementation of Finite Field Multipliers. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2952-2956 (2021) - 2020
- [j12]José Luis Imaña
High-throughput architecture for post-quantum DME cryptosystem. Integr. 75: 114-121 (2020) - [c6]José Luis Imaña
FPGA Implementation of Post-Quantum DME Cryptosystem. FCCM 2020: 209
2010 – 2019
- 2018
- [j11]José Luis Imaña
Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials. IEEE Trans. Computers 67(6): 898-904 (2018) - [c5]José Luis Imaña
Reconfigurable implementation of GF(2m) bit-parallel multipliers. DATE 2018: 893-896 - [c4]José Luis Imaña
Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials. FCCM 2018: 222 - 2016
- [j10]José Luis Imaña
High-Speed Polynomial Basis Multipliers Over GF(2m) for Special Pentanomials. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(1): 58-69 (2016) - 2013
- [j9]José Luis Imaña
Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials. Integr. 46(2): 197-210 (2013) - [j8]Gustavo Sutter
Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations. IEEE Trans. Ind. Electron. 60(1): 217-225 (2013) - 2012
- [j7]José Luis Imaña
Efficient Polynomial Basis Multipliers for Type-II Irreducible Pentanomials. IEEE Trans. Circuits Syst. II Express Briefs 59-II(11): 795-799 (2012) - 2011
- [j6]José Luis Imaña
Low Latency GF(2m) Polynomial Basis Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(5): 935-946 (2011) - [j5]Gustavo Sutter
Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation. IEEE Trans. Ind. Electron. 58(7): 3101-3109 (2011) - 2010
- [j4]José Luis Imaña
Probabilistic Verification over GF(2m) Using Mod2-OBDDs. Intell. Inf. Manag. 2(2): 95-103 (2010) - [c3]Gustavo Sutter
Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation. FPL 2010: 496-501
2000 – 2009
- 2008
- [e1]Joachim von zur Gathen, José Luis Imaña, Çetin Kaya Koç:
Arithmetic of Finite Fields, 2nd International Workshop, WAIFI 2008, Siena, Italy, July 6-9, 2008, Proceedings. Lecture Notes in Computer Science 5130, Springer 2008, ISBN 978-3-540-69498-4 [contents] - 2006
- [j3]José Luis Imaña
Bit-Parallel Finite Field Multipliers for Irreducible Trinomials. IEEE Trans. Computers 55(5): 520-533 (2006) - [j2]José Luis Imaña
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1388-1393 (2006) - [j1]José Luis Imaña
Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs. J. VLSI Signal Process. 42(3): 285-296 (2006) - 2004
- [c2]José Luis Imaña:
Reconfigurable implementation of bit-parallel multipliers over GF(2m) for two classes of finite fields. FPT 2004: 287-290 - 2003
- [c1]José Luis Imaña
A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2m). FPL 2003: 1127-1130
Coauthor Index
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