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Anh-Tuan Hoang
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2020 – today
- 2024
- [c13]Anh-Tuan Hoang, Mark Kennaway, Dung Tuan Pham, Thai Son Mai, Ayesha Khalid, Ciara Rafferty, Máire O'Neill:
Deep Learning Enhanced Side Channel Analysis on CRYSTALS-Kyber. ISQED 2024: 1-8 - 2022
- [c12]Anh-Tuan Hoang, Neil Hanley, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill:
Stacked Ensemble Models Evaluation on DL Based SCA. ICSBT/SECRYPT (Revised Selected Papers) 2022: 43-68 - [c11]Anh-Tuan Hoang, Neil Hanley, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill:
Stacked Ensemble Model for Enhancing the DL based SCA. SECRYPT 2022: 59-68 - 2020
- [j2]Anh-Tuan Hoang, Neil Hanley, Máire O'Neill:
Plaintext: A Missing Feature for Enhancing the Power of Deep Learning in Side-Channel Analysis? Breaking multiple layers of side-channel countermeasures. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020(4): 49-85 (2020)
2010 – 2019
- 2015
- [c10]Takumi Okamoto, Tetsushi Koide, Koki Sugi, Tatsuya Shimizu, Anh-Tuan Hoang, Toru Tamaki
, Bisser Raytchev
Image segmentation of pyramid style identifier based on Support Vector Machine for colorectal endoscopic images. EMBC 2015: 2997-3000 - 2014
- [j1]Anh-Tuan Hoang, Takeshi Fujino:
Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA. ACM Trans. Reconfigurable Technol. Syst. 7(2): 10:1-10:19 (2014) - [c9]Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto:
Low cost hardware implementation for traffic sign detection system. APCCAS 2014: 363-366 - [c8]Tetsushi Koide, Anh-Tuan Hoang, Takumi Okamoto, Satoshi Shigemi, Tsubasa Mishima, Toru Tamaki
FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification. APCCAS 2014: 651-654 - [c7]Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto, Mutsumi Omori:
Pipeline scanning architecture with computation reduction for rectangle pattern matching in real-time traffic sign detection. ISCAS 2014: 1532-1535 - [c6]Tsubasa Mishima, Satoshi Shigemi, Anh-Tuan Hoang, Tetsushi Koide, Toru Tamaki
FPGA implementation of feature extraction for colorectal endoscopic images with NBI magnification. ISCAS 2014: 2515-2518 - [c5]Masaharu Yamamoto, Anh-Tuan Hoang, Mutsumi Omori, Tetsushi Koide:
Compact hardware oriented number recognition algorithm for real-time speed traffic-sign recognition. ISCAS 2014: 2535-2538 - 2013
- [c4]Anh-Tuan Hoang, Takeshi Fujino:
Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only). FPGA 2013: 266-267 - 2012
- [c3]Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang, Takeshi Fujino:
Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. DSD 2012: 735-738 - [c2]Anh-Tuan Hoang, Takeshi Fujino:
Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. FPGA 2012: 1-10 - 2011
- [c1]Katsuhiko Iwai, Mitsuru Shiozaki, Anh-Tuan Hoang, Kenji Kojima, Takeshi Fujino:
Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL. HOST 2011: 28-33
Coauthor Index
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