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Raúl Mateos
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2020 – today
- 2020
- [j11]Rubén Nieto
, Raúl Mateos
Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution. IEEE Access 8: 188552-188563 (2020) - [j10]Rubén Nieto
HW/SW Architecture for a Broadband Power-Line Communication System With LS Channel Estimator and ASCET Equalizer. IEEE Trans. Ind. Informatics 16(11): 6740-6749 (2020) - [c11]Rubén Nieto
Evaluation of Software Inter-Processor Synchronization Methods for the Zynq-UltraScale+ Architecture. DCIS 2020: 1-6
2010 – 2019
- 2019
- [j9]Francisco Nombela, Enrique García, Raúl Mateos, Álvaro Hernández:
Real-time architecture for channel estimation and equalization in broadband PLC. Microprocess. Microsystems 65: 121-135 (2019) - [j8]Javier Moriano
Distortion-Free Instantaneous Multifrequency Saturator for THD Current Reduction. IEEE Trans. Ind. Electron. 66(7): 5310-5320 (2019) - [c10]Rubén Nieto
Dual-Core Architecture for PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer. ETFA 2019: 1342-1345 - [c9]Edel Díaz, Raúl Mateos, Emilio José Bueno:
Virtual Platform of FPGA based MPSoC for Power Electronics Applications: OS simulation. IECON 2019: 3118-3123 - [c8]Edel Díaz, Raúl Mateos, Emilio José Bueno:
Virtual Platform of FPGA based SoC for Power Electronics Applications. ISIE 2019: 1371-1376 - 2018
- [j7]Pablo Poudereux, Álvaro Hernández, Fernando Cruz-Roldán
FPGA-Based Architecture for Medium Access Techniques in Broadband PLC. IEEE Access 6: 9534-9542 (2018) - [c7]Rubén Nieto
Finite Precision Analysis of FPGA-based Architecture for FBMC Transmultiplexers in Broadband PLC. DCIS 2018: 1-6 - 2016
- [j6]Pablo Poudereux, Álvaro Hernández, Raúl Mateos, Freddy A. Pinto-Benel, Fernando Cruz-Roldán
Design of a filter bank multi-carrier system for broadband power line communications. Signal Process. 128: 57-67 (2016) - 2015
- [j5]Francisco Nombela, Enrique García, Raúl Mateos, Álvaro Hernández:
Efficient Implementation of a Symbol Timing Estimator for Broadband PLC. Sensors 15(8): 20825-20844 (2015) - [c6]Pablo Poudereux, Raúl Mateos, Álvaro Hernández, Francisco Nombela, Fernando Cruz-Roldán:
Study of suitable filter architectures for FBMC techniques applied to PLC communications. ETFA 2015: 1-6 - 2014
- [c5]Pablo Poudereux, Raúl Mateos, Álvaro Hernández, Fernando Cruz-Roldán
FPGA-based implementation of a filter bank-based transmultiplexer for multicarrier communications. ETFA 2014: 1-6 - 2013
- [c4]Fco. Manuel Sánchez, Raúl Mateos, Emilio José Bueno, Javier Mingo, Ines Sanz:
Comparative of HLS and HDL implementations of a grid synchronization algorithm. IECON 2013: 2232-2237 - 2010
- [j4]Jorge Camacho
A Strict-Time Distributed Architecture for Digital Beamforming of Ultrasound Signals. IEEE Trans. Instrum. Meas. 59(10): 2716-2723 (2010)
2000 – 2009
- 2009
- [j3]Emilio José Bueno, Álvaro Hernández, Francisco J. Rodríguez
A DSP- and FPGA-Based Industrial Control With High-Speed Communication Interfaces for Grid Converters Applied to Distributed Power Generation Systems. IEEE Trans. Ind. Electron. 56(3): 654-669 (2009) - 2004
- [c3]Raúl Mateos, José Luis Lázaro, Felipe Espinosa:
Hardware/software co-simulation environment for CSoC with soft processors. FPT 2004: 445-448 - 2003
- [c2]Raúl Mateos, Alfredo Gardel Vicente
Lossless implementation in VHDL of an image wavelet transform. ETFA (2) 2003: 195-198 - [c1]Ignacio Bravo Muñoz
Different proposals to the multiplication of 3×3 vision mask in VHDL for FPGA's. ETFA (2) 2003: 208-211 - 2001
- [j2]Felipe Espinosa, Elena López Guillén, Raúl Mateos, Manuel Mazo, Ricardo García:
Advanced and Intelligent Control Techniques Applied to the Drive Control and Path Tracking Systems on a Robotic Wheelchair. Auton. Robots 11(2): 137-148 (2001) - [j1]José Luis Lázaro, Alfredo Gardel Vicente
Mobile Robot with Wide Capture Active Laser Sensor and Environment Definition. J. Intell. Robotic Syst. 30(3): 227-248 (2001)
Coauthor Index
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