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Mohammad Reza Reshadinezhad
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2020 – today
- 2024
- [j12]Samane Asgari, Mohammad Reza Reshadinezhad
, Seyed Erfan Fatemieh
Energy-efficient and fast IMPLY-based approximate full adder applying NAND gates for image processing. Comput. Electr. Eng. 113: 109053 (2024) - [j11]Sarallah Keshavarz, Mohammad Reza Reshadinezhad, Shekoofeh Moghimi:
T-count and T-depth efficient fault-tolerant quantum arithmetic and logic unit. Quantum Inf. Process. 23(7): 245 (2024) - [j10]Fatemeh Kazemi HassanAbadi
Cascadable-Controllable Self-Assembly DNA Tiles for Large-Scale DNA Logic Circuits. IEEE Trans. Biomed. Circuits Syst. 18(3): 478-497 (2024) - [j9]Shekoofeh Moghimi
Toward Designing High-Speed Cost-Efficient Quantum Reversible Carry Select Adders. IEEE Trans. Emerg. Top. Comput. 12(3): 905-917 (2024) - [j8]Samira Shirinabadi Farahani, Mohammad Reza Reshadinezhad, Seyed Erfan Fatemieh:
New design for error-resilient approximate multipliers used in image processing in CNTFET technology. J. Supercomput. 80(3): 3694-3712 (2024) - [i3]Seyed Erfan Fatemieh, Mohammad Reza Reshadinezhad:
Energy-Efficient Approximate Full Adders Applying Memristive Serial IMPLY Logic For Image Processing. CoRR abs/2406.05525 (2024) - [i2]Bahareh Bagheralmoosavi, Seyed Erfan Fatemieh, Mohammad Reza Reshadinezhad, Antonio Rubio:
Power-Area Efficient Serial IMPLY-based 4:2 Compressor Applied in Data-Intensive Applications. CoRR abs/2407.09980 (2024) - [i1]Seyed Erfan Fatemieh, Bahareh Bagheralmoosavi, Mohammad Reza Reshadinezhad:
Energy-Efficient and Fast Memristor-based Serial Multipliers Applicable in Image Processing. CoRR abs/2410.09953 (2024) - 2023
- [j7]Seyed Erfan Fatemieh
Fast and Compact Serial IMPLY-Based Approximate Full Adders Applied in Image Processing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 175-188 (2023) - 2022
- [c2]Seyed Erfan Fatemieh, Mohammad Reza Reshadinezhad, Nima TaheriNejad:
Approximate In-Memory Computing using Memristive IMPLY Logic and its Application to Image Processing. ISCAS 2022: 3115-3119 - 2021
- [j6]Seyed Erfan Fatemieh
LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS. Sustain. Comput. Informatics Syst. 30: 100529 (2021) - 2020
- [j5]Arezoo Dabaghi Zarandi, Mohammad Reza Reshadinezhad
A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells. IEEE Access 8: 58585-58593 (2020) - [c1]Arezoo Dabaghi Zarandi, Antonio Rubio, Mohammad Reza Reshadinezhad:
A Memristor-based Quaternary Memory with Adaptive Noise Tolerance. DCIS 2020: 1-6
2010 – 2019
- 2019
- [j4]Seyyed Ashkan Ebrahimi, Mohammad Reza Reshadinezhad
A new design method for imperfection-immune CNFET-based circuit design. Microelectron. J. 85: 62-71 (2019) - 2018
- [j3]Shiva Rahbar Arabani, Mohammad Reza Reshadinezhad, Majid Haghparast:
Design of a parity preserving reversible full adder/subtractor circuit. Int. J. Comput. Intell. Stud. 7(1): 19-32 (2018) - 2016
- [j2]Seyyed Ashkan Ebrahimi, Mohammad Reza Reshadinezhad
Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits. Microelectron. J. 53: 156-166 (2016) - 2012
- [j1]Mohammad Reza Reshadinezhad
An Energy-Efficient Full Adder Cell Using CNFET Technology. IEICE Trans. Electron. 95-C(4): 744-751 (2012)
Coauthor Index
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