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Tiantian Liu 0001
Person information
- affiliation: Chinese Academy of Sciences, Cloud Computing Center, Dongguan, China
- affiliation (PhD 2012): City University of Hong Kong, Department of Computer Science, Kowloon, Hong Kong
Other persons with the same name
- Tiantian Liu (aka: Tian-Tian Liu) — disambiguation page
- Tiantian Liu 0002
— Zhejiang University, Hangzhou, China (and 3 more)
- Tiantian Liu 0003
- Tiantian Liu 0004
- Tiantian Liu 0006
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2020 – today
- 2022
- [j10]Weifan Sun, Wei Fan, Mengying Zhao
Deep Reinforcement-Learning-Guided Backup for Energy Harvesting Powered Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(2): 346-358 (2022)
2010 – 2019
- 2017
- [j9]Mengying Zhao, Yuan Xue, Jingtong Hu
State Asymmetry Driven State Remapping in Phase Change Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 27-40 (2017) - 2013
- [j8]Tiantian Liu, Chun Jason Xue
Joint variable partitioning and bank selection instruction optimization for partitioned memory architectures. ACM Trans. Embed. Comput. Syst. 12(3): 76:1-76:27 (2013) - [j7]Tiantian Liu, Alex Orailoglu, Chun Jason Xue
Register allocation for embedded systems to simultaneously reduce energy and temperature on registers. ACM Trans. Embed. Comput. Syst. 13(3): 50:1-50:26 (2013) - [j6]Tiantian Liu, Yingchao Zhao
Power-Aware Variable Partitioning for DSPs With Hybrid PRAM and DRAM Main Memory. IEEE Trans. Signal Process. 61(14): 3509-3520 (2013) - 2012
- [j5]Minming Li
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture. J. Comb. Optim. 23(2): 274-291 (2012) - [j4]Yazhi Huang, Tiantian Liu, Chun Jason Xue
Register allocation for write activity minimization on non-volatile main memory for embedded systems. J. Syst. Archit. 58(1): 13-23 (2012) - [j3]Tiantian Liu, Minming Li
Instruction cache locking for multi-task real-time embedded systems. Real Time Syst. 48(2): 166-197 (2012) - [j2]Tiantian Liu, Minming Li
Instruction Cache Locking for Embedded Systems using Probability Profile. J. Signal Process. Syst. 69(2): 173-188 (2012) - 2011
- [j1]Tiantian Liu, Yingchao Zhao
Joint task assignment and cache partitioning with cache locking for WCET minimization on MPSoC. J. Parallel Distributed Comput. 71(11): 1473-1483 (2011) - [c9]Yazhi Huang, Tiantian Liu, Chun Jason Xue
Register allocation for write activity minimization on non-volatile main memory. ASP-DAC 2011: 129-134 - [c8]Tiantian Liu, Yingchao Zhao
Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory. DAC 2011: 405-410 - [c7]Tiantian Liu, Alex Orailoglu, Chun Jason Xue, Minming Li:
Register allocation for simultaneous reduction of energy and peak temperature on registers. DATE 2011: 20-25 - 2010
- [c6]Tiantian Liu, Minming Li
Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks. ASP-DAC 2010: 113-118 - [c5]Tiantian Liu, Yingchao Zhao
Task Assignment with Cache Partitioning and Locking for WCET Minimization on MPSoC. ICPP 2010: 573-582 - [c4]Minming Li
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture. LCTES 2010: 1-8
2000 – 2009
- 2009
- [c3]Tiantian Liu, Minming Li
Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking. IEEE Real-Time and Embedded Technology and Applications Symposium 2009: 35-44 - [c2]Tiantian Liu, Minming Li
Instruction Cache Locking for Real-Time Embedded Systems with Multi-tasks. RTCSA 2009: 494-499 - 2008
- [c1]Chun Jason Xue
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks. ICASSP 2008: 1453-1456
Coauthor Index
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