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Bernhard Hoppe
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2010 – 2019
- 2012
- [j2]Anja Lina Müller, Andreas Schwarzbacher, Bernhard Hoppe:
Opening a M. Sc. in Electrical Engineering for non-traditional Students. Int. J. Adv. Corp. Learn. 5(2): 15-19 (2012) - [c9]Anja Lina Müller, Bernhard Hoppe, Andreas Schwarzbacher:
Opening a M. Sc. in electrical engineering for non-traditional students. EDUCON 2012: 1-6
2000 – 2009
- 2007
- [c8]Christian Jakob, A. Th. Schwarzbacher, Bernhard Hoppe, Reiner Peters:
A FPGA Optimised Digital Real-Time Mutichannel Correlator Architecture. DSD 2007: 35-42 - [c7]Christian Jakob, A. Th. Schwarzbacher, Bernhard Hoppe, Reiner Peters:
A Multichannel Digital Real-Time Correlator as Single FPGA Implementation. DSP 2007: 276-279 - 2004
- [c6]Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe:
FPGA-Efficient Hybrid LUT/CORDIC Architecture. FPL 2004: 933-937 - [c5]Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe:
FPGA-efficient phase-to-I/Q architecture. SoCC 2004: 373-376 - 2002
- [c4]Ireneusz Janiszewski, Bernhard Hoppe, Hermann Meuth:
Modelling and Simulation in the Design Flow for Numerically Controlled Oscillators. ESM 2002: 625-629 - 2001
- [c3]Ireneusz Janiszewski, Bernhard Hoppe, Hermann Meuth:
VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers. DAC 2001: 573-578
1990 – 1999
- 1999
- [c2]Martin Engels, Bernhard Hoppe, Hermann Meuth, Reiner Peters:
A single chip 200 MHz digital correlation system for laser spectroscopy with 512 correlation channels. ISCAS (5) 1999: 160-163 - 1990
- [j1]Bernhard Hoppe, Gerd Neuendorf, Doris Schmitt-Landsiedel, J. Will Specks:
Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 236-247 (1990) - [c1]Veronika Eisele, Bernhard Hoppe, Oliver Kiehl:
Transmission gate delay models for circuit optimization. EURO-DAC 1990: 558-562
Coauthor Index
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