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Jean-Pierre David
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2020 – today
- 2024
- [j22]Nizar El Zarif
, MohammadHossein AskariHemmat, Théo Dupuis, Jean-Pierre David
Polara-Keras2c: Supporting Vectorized AI Models on RISC-V Edge Devices. IEEE Access 12: 171836-171852 (2024) - [j21]Mostafa Elbediwy
DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In-First-Out Queue. IEEE Trans. Netw. Serv. Manag. 21(1): 355-371 (2024) - [c55]Tzu-Yi Chiu, Jerome Le Ny, Jean-Pierre David:
Temporal Logic Explanations for Dynamic Decision Systems Using Anchors and Monte Carlo Tree Search (Abstract Reprint). AAAI 2024: 22694 - [c54]Aymen-Alaeddine Zeghaida, Dinesh Daultani, J. M. Pierre Langlois, Jean-Pierre David:
Scalable Low-Complexity Implementation of Constant Matrix Multiplication Circuits. MWSCAS 2024: 357-361 - [c53]Elisabeth Humblet, Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria:
MSPARQ: A RISC-V Vector Processor Array Optimized for Low-Resolution Neural Networks. MWSCAS 2024: 464-468 - [c52]Karim Kaced, Sebastien Genevey, Yvon Savaria, Jean-Pierre David:
A Flexible Thermal/Solar Energy Harvesting System with Hysteretic Control and Maximum Power Point Tracking Regulation for IoT Devices. NewCAS 2024: 323-327 - [i8]MohammadHossein AskariHemmat, Ahmadreza Jeddi, Reyhane Askari Hemmat, Ivan Lazarevich, Alexander Hoffman, Sudhakar Sah, Ehsan Saboori, Yvon Savaria, Jean-Pierre David:
QGen: On the Ability to Generalize in Quantization Aware Training. CoRR abs/2404.11769 (2024) - 2023
- [j20]Mostafa Elbediwy
A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. IEEE Access 11: 61422-61436 (2023) - [j19]Tzu-Yi Chiu
Temporal logic explanations for dynamic decision systems using anchors and Monte Carlo Tree Search. Artif. Intell. 318: 103897 (2023) - [j18]Kamran Chitsaz, Gonçalo Mordido, Jean-Pierre David, François Leduc-Primeau:
Training DNNs Resilient to Adversarial and Random Bit-Flips by Learning Quantization Ranges. Trans. Mach. Learn. Res. 2023 (2023) - [c51]Mohammadhossein Askarihemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David:
BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU. ASP-DAC 2023: 483-489 - [c50]MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David:
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. ISCAS 2023: 1-5 - [c49]Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, Nizar El Zarif, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria:
Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference. NEWCAS 2023: 1-5 - [c48]Amirali Ebrahimi, Vineeth Narayan Pullu, J. M. Pierre Langlois, Jean-Pierre David:
Iterative pruning algorithm for efficient look-up table implementation of binary neural networks. NEWCAS 2023: 1-5 - [c47]Dufour Jules, Yvon Savaria, Jean-Pierre David:
Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries. NEWCAS 2023: 1-5 - [i7]Mohammadhossein Askarihemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David:
BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU. CoRR abs/2301.00290 (2023) - [i6]MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. CoRR abs/2302.05996 (2023) - [i5]Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, Nizar El Zarif, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria:
Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference. CoRR abs/2306.09905 (2023) - 2022
- [c46]Mengyue Su, Jean-Pierre David, Yvon Savaria, Bill Pontikakis, Thomas Luinaud:
An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices. ISCAS 2022: 2529-2533 - [c45]Jörg Ehmer, Bertrand Granado, Julien Denoulet, Yvon Savaria, Jean-Pierre David:
Low Complexity Shallow Neural Network With Improved False Negative Rate for Cyber Intrusion Detection Systems. NEWCAS 2022: 168-172 - [c44]Moussa Traore, J. M. Pierre Langlois, Jean-Pierre David:
ASIP Accelerator for LUT-based Neural Networks Inference. NEWCAS 2022: 524-528 - [i4]MohammadHossein AskariHemmat, Reyhane Askari Hemmat, Alexander Hoffman, Ivan Lazarevich, Ehsan Saboori, Olivier Mastropietro, Yvon Savaria, Jean-Pierre David:
QReg: On Regularization Effects of Quantization. CoRR abs/2206.12372 (2022) - 2021
- [j17]Jean-Pierre David, Manuel J. Barragán:
Guest Editorial Special Issue on the IEEE International NEWCAS Conference 2020. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3131-3132 (2021) - [c43]MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David:
RISC-V Barrel Processor for Deep Neural Network Acceleration. ISCAS 2021: 1-5 - 2020
- [j16]Aref Trigui
Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique. IEEE Trans. Circuits Syst. 67-I(11): 3978-3990 (2020) - [j15]Ahmed M. Abdelsalam
POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees. J. Signal Process. Syst. 92(1): 95-107 (2020) - [c42]MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David:
RISC-V Barrel Processor for Accelerator Control. FCCM 2020: 212 - [c41]Sivakumar Chidambaram, Pierre Langlois, Jean-Pierre David:
PoET-BiN: Power Efficient Tiny Binary Neurons. MLSys 2020 - [p1]Simon Pierre Boyogueno Bidias, Jean-Pierre David, Yvon Savaria, Réjean Plamondon:
On the Use of Interval Arithmetic for the Branch and Bound Delta-Lognormal Parameter Extraction of Rapid Human Movements. The Lognormality Principle 2020: 309-325 - [i3]Sivakumar Chidambaram, J. M. Pierre Langlois, Jean-Pierre David:
PoET-BiN: Power Efficient Tiny Binary Neurons. CoRR abs/2002.09794 (2020)
2010 – 2019
- 2019
- [c40]Federico Montano, Tarek Ould-Bachir
A Low-Latency Reconfigurable Multistage Interconnection Network. CCECE 2019: 1-4 - [c39]Ahmed M. Abdelsalam, Ahmed Elsheikh, Jean-Pierre David, J. M. Pierre Langlois:
POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests. DASIP 2019: 13-18 - [c38]Alexandre Riviello, Jean-Pierre David:
Binary Speech Features for Keyword Spotting Tasks. INTERSPEECH 2019: 3460-3464 - [c37]Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David:
Bit-Slicing FPGA Accelerator for Quantized Neural Networks. ISCAS 2019: 1-5 - [c36]MohammadHossein AskariHemmat, Sina Honari, Lucas Rouhier, Christian S. Perone, Julien Cohen-Adad, Yvon Savaria, Jean-Pierre David:
U-Net Fixed-Point Quantization for Medical Image Segmentation. LABELS/HAL-MICCAI/CuRIOUS@MICCAI 2019: 115-124 - [i2]MohammadHossein AskariHemmat, Sina Honari, Lucas Rouhier, Christian S. Perone, Julien Cohen-Adad, Yvon Savaria, Jean-Pierre David:
U-Net Fixed-Point Quantization for Medical Image Segmentation. CoRR abs/1908.01073 (2019) - 2018
- [j14]Michel Gemieux, Meng Li
A Hybrid Architecture With Low Latency Interfaces Enabling Dynamic Cache Management. IEEE Access 6: 62826-62839 (2018) - [j13]Roberto Sanchez Correa, Jean-Pierre David:
Ultra-low latency communication channels for FPGA-based HPC cluster. Integr. 63: 41-55 (2018) - [j12]Federico Montano
An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters. IEEE Trans. Ind. Electron. 65(1): 636-644 (2018) - [j11]Marc-André Daigneault, Jean-Pierre David:
Automated Synthesis of Streaming Transfer Level Hardware Designs. ACM Trans. Reconfigurable Technol. Syst. 11(2): 13:1-13:22 (2018) - [c35]Ahmed M. Abdelsalam, Ahmed Elsheikh, Jean-Pierre David, J. M. Pierre Langlois:
POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA. DASIP 2018: 19-24 - [c34]Sivakumar Chidambaram, Alexandre Riviello, J. M. Pierre Langlois, Jean-Pierre David:
Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors. DASIP 2018: 94-99 - 2017
- [j10]Jean-Pierre David:
Low latency and division free Gauss-Jordan solver in floating point arithmetic. J. Parallel Distributed Comput. 106: 185-193 (2017) - [c33]Michel Gemieux, Yvon Savaria, Jean-Pierre David, Guchuan Zhu:
A Cache-Coherent Heterogeneous Architecture for Low Latency Real Time Applications. ISORC 2017: 176-184 - [c32]Himan Khanzadi, Yvon Savaria, Jean-Pierre David:
A data driven CGRA Overlay Architecture with embedded processors. NEWCAS 2017: 269-272 - 2015
- [c31]Himan Khanzadi, Yvon Savaria, Jean-Pierre David:
Mapping applications on two-level configurable hardware. AHS 2015: 1-8 - [c30]Marc-André Daigneault, Jean-Pierre David:
Intermediate-Level Synthesis of a Gauss-Jordan Elimination Linear Solver. IPDPS Workshops 2015: 176-181 - [c29]Matthieu Courbariaux, Yoshua Bengio, Jean-Pierre David:
BinaryConnect: Training Deep Neural Networks with binary weights during propagations. NIPS 2015: 3123-3131 - [c28]Jean-Pierre David:
Low latency solver for linear equation systems in floating point arithmetic. ReConFig 2015: 1-7 - [c27]Matthieu Courbariaux, Yoshua Bengio, Jean-Pierre David:
Low precision arithmetic for deep learning. ICLR (Workshop) 2015 - [i1]Matthieu Courbariaux, Yoshua Bengio, Jean-Pierre David:
BinaryConnect: Training Deep Neural Networks with binary weights during propagations. CoRR abs/1511.00363 (2015) - 2014
- [j9]Marc-André Daigneault, Jean-Pierre David:
Fast description and synthesis of control-dominant circuits. Comput. Electr. Eng. 40(4): 1199-1214 (2014) - 2013
- [j8]Tarek Ould-Bachir
A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits. Math. Comput. Simul. 91: 167-177 (2013) - [j7]Tarek Ould-Bachir
Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators. ACM Trans. Reconfigurable Technol. Syst. 6(1): 1:1-1:21 (2013) - [c26]Marc-André Daigneault, Jean-Pierre David:
High-Level Description and Synthesis of Floating-Point Accumulators on FPGA. FCCM 2013: 206-209 - [c25]Marc-André Daigneault, Jean-Pierre David:
Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only). FPGA 2013: 274-275 - [c24]Jean-Pierre David:
Max-hashing fragments for large data sets detection. ReConFig 2013: 1-6 - 2012
- [j6]Hugo Fortin-Blanchette, Tarek Ould-Bachir
A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters. IEEE Trans. Ind. Electron. 59(12): 4555-4567 (2012) - [c23]Marc-André Daigneault, Jean-Pierre David:
Raising the abstraction level of HDL for control-dominant applications. FPL 2012: 515-518 - [c22]Mathieu Allard, Patrick Grogan, Yvon Savaria, Jean-Pierre David:
Two-level configuration for FPGA: A new design methodology based on a computing fabric. ISCAS 2012: 265-268 - [c21]Tarek Ould-Bachir
Effective floating-point calculation engines intended for the FPGA-based HIL simulation. ISIE 2012: 1363-1368 - [c20]Marc-André Daigneault, Jean-Pierre David:
Synchronized-transfer-level design methodology applied to hardware matrix multiplication. ReConFig 2012: 1-7 - 2011
- [j5]Marc-André Daigneault, Jean-Pierre David:
A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration. IEEE Trans. Instrum. Meas. 60(6): 2070-2079 (2011) - [j4]Etienne Bergeron, Louis-David Perron, Marc Feeley, Jean-Pierre David:
Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation. ACM Trans. Reconfigurable Technol. Syst. 4(2): 12:1-12:27 (2011) - 2010
- [c19]Tarek Ould Bachir
Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision. FCCM 2010: 105-108 - [c18]Marc-André Daigneault, Jean-Pierre David:
Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only). FPGA 2010: 283
2000 – 2009
- 2009
- [c17]Mathieu Allard, Patrick Grogan, Jean-Pierre David:
A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA. ReConFig 2009: 107-112 - 2008
- [j3]A. Gauffier, Jean-Pierre David, Olivier Gilard:
Analytical model for multi-junction solar cells prediction in space environment. Microelectron. Reliab. 48(8-9): 1494-1499 (2008) - [c16]Etienne Bergeron, Marc Feeley, Jean-Pierre David:
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs. CC 2008: 178-192 - [c15]Jean-Michel Adam, Anne Lejeune, Sandra Michelet, Jean-Pierre David, Christian Martel:
Setting up On-Line Learning Experiments: The LearningLab Platform. ICALT 2008: 761-763 - [c14]Marc-André Daigneault, J. M. Pierre Langlois, Jean-Pierre David:
Application Specific Instruction set processor specialized for block motion estimation. ICCD 2008: 266-271 - 2007
- [j2]Jean-Pierre David, Kassem Kalach, Nicolas Tittley:
Hardware Complexity of Modular Multiplication and Exponentiation. IEEE Trans. Computers 56(10): 1308-1319 (2007) - 2006
- [c13]Emmanuelle Villiot-Leclercq, Jean-Pierre David, Anne Lejeune:
Expressing Learning Scenarios with Computer Independent Models. ICALT 2006: 520-522 - [c12]Christian Martel, Laurence Vignollet, Christine Ferraris, Jean-Pierre David, Anne Lejeune:
Modeling Collaborative Learning Activities on e-Learning Platforms. ICALT 2006: 707-709 - [c11]Christian Martel, Laurence Vignollet, Christine Ferraris, Jean-Pierre David, Anne Lejeune:
LDL: An Alternative EML. ICALT 2006: 1107-1108 - [c10]Laurence Vignollet, Jean-Pierre David, Christine Ferraris, Christian Martel, Anne Lejeune:
Comparing Educational Modeling Languages on a Case Study. ICALT 2006: 1149-1151 - [c9]Jean-Pierre David, Anne Lejeune, Emmanuelle Villiot-Leclercq:
Expressing Workshop Scenario with Computer Independent Model. ICALT 2006: 1168-1169 - 2005
- [c8]Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley, Jean-Pierre David:
High Level Synthesis for Data-Driven Applications. IEEE International Workshop on Rapid System Prototyping 2005: 54-60 - 2004
- [c7]Jean-Pierre David, Etienne Bergeron:
An Intermediate Level HDL for System Level Design. FDL 2004: 526-536 - [c6]Jean-Pierre David, Etienne Bergeron:
A Step towards Intelligent Translation from High-Level Design to RTL. IWSOC 2004: 183-188 - 2002
- [c5]Jean-Jacques Quisquater, François-Xavier Standaert, Gaël Rouvroy, Jean-Pierre David, Jean-Didier Legat:
A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation. FPL 2002: 780-789 - [c4]François Koeune, Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Pierre David, Jean-Didier Legat:
An FPGA Implementation of the Linear Cryptanalysis. FPL 2002: 845-852 - 2001
- [c3]Jean-Pierre David, Tony Postiau, Paul Fisette, Jean-Didier Legat:
Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications. IPDPS 2001: 143
1990 – 1999
- 1998
- [c2]Jean-Pierre David, Jean-Didier Legat:
A Data-Flow Oriented Co-Design for Reconfigurable Systems. International Workshop on Rapid System Prototyping 1998: 207-211 - 1996
- [c1]Jean-Pierre David, André Cogne, Annick Dutel:
Hypermedia Exercises Prototyping and Modelising. CALISCE 1996: 252-260 - 1994
- [j1]Viviane Guéraud, Jean-Michel Cagnat, Jean-Pierre David, Jean-Philippe Pernin:
Software environments for computer aided education. ACM SIGCSE Bull. 26(2): 19-25 (1994)
Coauthor Index
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last updated on 2024-12-02 21:24 CET by the dblp team
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