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Konstantin Moiseev
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2010 – 2019
- 2015
- [j7]Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. Integr. 48: 116-128 (2015) - 2012
- [j6]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
The complexity of VLSI power-delay optimization by interconnect resizing. J. Comb. Optim. 23(2): 292-300 (2012) - 2010
- [j5]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Interconnect Bundle Sizing Under Discrete Design Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1650-1654 (2010) - [c2]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Interconnect power and delay optimization by dynamic programming in gridded design rules. ISPD 2010: 153-160
2000 – 2009
- 2009
- [j4]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Power-delay optimization in VLSI microprocessors by wire spacing. ACM Trans. Design Autom. Electr. Syst. 14(4): 55:1-55:28 (2009) - 2008
- [j3]Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
On optimal ordering of signals in parallel wire bundles. Integr. 41(2): 253-268 (2008) - [j2]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Timing-aware power-optimal ordering of signals. ACM Trans. Design Autom. Electr. Syst. 13(4): 65:1-65:17 (2008) - 2006
- [j1]Shmuel Wimer, Shay Michaely, Konstantin Moiseev, Avinoam Kolodny:
Optimal bus sizing in migration of processor design. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 1089-1100 (2006) - [c1]Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. ISCAS 2006
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