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Andrew E. Caldwell
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2000 – 2009
- 2004
- [j9]Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong:
Effective iterative techniques for fingerprinting design IP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2): 208-215 (2004) - 2003
- [j8]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Hierarchical whitespace allocation in top-down placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1550-1556 (2003) - 2002
- [j7]Andrew E. Caldwell, Igor L. Markov:
Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms. IEEE Des. Test Comput. 19(3): 72-81 (2002) - 2000
- [j6]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning. ACM J. Exp. Algorithmics 5: 5 (2000) - [j5]Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Hypergraph partitioning with fixed vertices [VLSI CAD]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 267-272 (2000) - [j4]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Optimal partitioners and end-case placers for standard-cell layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1304-1313 (2000) - [j3]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Iterative Partitioning with Varying Node Weights. VLSI Design 11(3): 249-258 (2000) - [c11]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Improved algorithms for hypergraph bipartitioning. ASP-DAC 2000: 661-666 - [c10]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Can recursive bisection alone produce routable placements? DAC 2000: 477-482 - [c9]Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar
, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester:
GTX: the MARCO GSRC technology extrapolation system. DAC 2000: 693-698 - [c8]Marcelo O. Johann, Andrew E. Caldwell, Ricardo Augusto da Luz Reis, Andrew B. Kahng:
Admissibility Proofs for the LCS* Algorithm. IBERAMIA-SBIA 2000: 236-244
1990 – 1999
- 1999
- [j2]Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
On wirelength estimations for row-based placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1265-1278 (1999) - [j1]Charles J. Alpert, Andrew E. Caldwell, Tony F. Chan
Analytical Engines are Unnecessary in Top-down Partitioning-based Placement. VLSI Design 10(1): 99-116 (1999) - [c7]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning. ALENEX 1999: 177-193 - [c6]Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov:
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. DAC 1999: 349-354 - [c5]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Hypergraph Partitioning with Fixed Vertices. DAC 1999: 355-359 - [c4]Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong:
Effective Iterative Techniques for Fingerprinting Design IP. DAC 1999: 843-848 - [c3]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Optimal partitioners and end-case placers for standard-cell layout. ISPD 1999: 90-96 - [c2]Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Partitioning with terminals: a "new" problem and new benchmarks. ISPD 1999: 151-157 - 1998
- [c1]Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky:
On wirelength estimations for row-based placement. ISPD 1998: 4-11
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