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Matthew R. Wordeman
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2010 – 2019
- 2017
- [c5]Raphael Robertazzi, Micheal Scheurman, Matt Wordeman, Shurong Tian, Christy Tyberg:
Analytical test of 3D integrated circuits. ITC 2017: 1-10 - 2016
- [j12]Toshiaki Kirihata, John Golz, Matthew R. Wordeman, Pooja Batra, Gary W. Maier, Norman Robson, Troy L. Graves-abe, Daniel Berger, Subramanian S. Iyer:
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 373-384 (2016) - [c4]Michael Scheuermann, Shurong Tian, Raphael Robertazzi, Matthew R. Wordeman, C. Bergeron, H. Jacobson, Phillip J. Restle, Joel Silberman, Christy Tyberg:
Thermal analysis of multi-layer functional 3D logic stacks. 3DIC 2016: 1-4 - 2012
- [c3]Matt Wordeman, Joel Silberman, Gary W. Maier, Michael Scheuermann:
A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias. ISSCC 2012: 186-187 - [c2]Liang-Teck Pang, Phillip J. Restle, Matthew R. Wordeman, Joel A. Silberman, Robert L. Franch, Gary W. Maier:
A shorted global clock design for multi-GHz 3D stacked chips. VLSIC 2012: 170-171
2000 – 2009
- 2008
- [j11]Steven J. Koester
, Albert M. Young, Roy R. Yu, Sampath Purushothaman, Kuan-Neng Chen, Douglas C. La Tulipe Jr., Narender Rana, Leathen Shi, Matthew R. Wordeman, Edmund J. Sprogis:
Wafer-level 3D integration technology. IBM J. Res. Dev. 52(6): 583-597 (2008) - 2005
- [j10]Toshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer:
An 800-MHz embedded DRAM with a concurrent refresh mode. IEEE J. Solid State Circuits 40(6): 1377-1387 (2005) - 2000
- [j9]Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman:
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. IEEE J. Solid State Circuits 35(5): 713-718 (2000) - [j8]Osamu Takahashi, Sang H. Dhong, Manabu Ohkubo, Shohji Onishi, Robert H. Dennard, Robert Hannon, Scott Crowder, Subramanian S. Iyer, Matthew R. Wordeman, Bijan Davari, William B. Weinberger, Naoaki Aoki:
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro. IEEE J. Solid State Circuits 35(11): 1673-1679 (2000)
1990 – 1999
- 1999
- [j7]Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman:
A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. IEEE J. Solid State Circuits 34(11): 1580-1588 (1999) - 1998
- [j6]Toshiaki Kirihata, Martin Gall, Kohji Hosokawa
A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. IEEE J. Solid State Circuits 33(11): 1711-1719 (1998) - 1997
- [j5]Toshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik:
Flexible test mode approach for 256-Mb DRAM. IEEE J. Solid State Circuits 32(10): 1525-1534 (1997) - [c1]W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285 - 1996
- [j4]Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke
Fault-tolerant designs for 256 Mb DRAM. IEEE J. Solid State Circuits 31(4): 558-566 (1996) - [j3]Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii:
A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. IEEE J. Solid State Circuits 31(4): 567-574 (1996) - 1995
- [j2]Charles W. Koburger III, William F. Clark, James W. Adkisson, Eric Adler, Paul E. Bakeman, Albert S. Bergendahl, Alan B. Botula, W. Chang, Bijan Davari, John H. Givens, Howard H. Hansen, Steven J. Holmes, David V. Horak, Chung Hon Lam, Jerome B. Lasky, Stephen E. Luce, Randy W. Mann, Glen L. Miles, James S. Nakos, Edward J. Nowak, Ghavam G. Shahidi, Yuan Taur, Francis R. White, Matthew R. Wordeman:
A half-micron CMOS logic generation. IBM J. Res. Dev. 39(1-2): 215-228 (1995) - 1992
- [j1]Wai Lee, Steven E. Laux, Massimo V. Fischetti, Giorgio Baccarani, Antonio Gnudi, Johannes M. C. (Hans) Stork, Jack A. Mandelman, Emmanuel F. Crabbé, Matthew R. Wordeman, Farouk Odeh:
Numerical modeling of advanced semiconductor devices. IBM J. Res. Dev. 36(2): 208-232 (1992)
Coauthor Index
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