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Daniel Molka
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2010 – 2019
- 2017
- [b1]Daniel Molka:
Performance Analysis of Complex Shared Memory Systems. Dresden University of Technology, Germany, 2017 - [c19]Daniel Molka
, Robert Schöne, Daniel Hackenberg
Detecting Memory-Boundedness with Hardware Performance Counters. ICPE 2017: 27-38 - 2016
- [j6]Wolfgang E. Nagel, Daniel Molka, Thomas Ludwig, Matthias S. Müller
Editorial for the special issue on Energy-aware high performance computing. Comput. Sci. Res. Dev. 31(4): 163-164 (2016) - [c18]Robert Schöne, Thomas Ilsche, Mario Bielert, Daniel Molka, Daniel Hackenberg:
Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors. E2SC@SC 2016: 69-76 - 2015
- [j5]Wolfgang E. Nagel, Daniel Molka, Thomas Ludwig, Matthias S. Müller
Editorial for the fifth international conference on energy-aware high performance computing. Comput. Sci. Res. Dev. 30(2): 105-106 (2015) - [j4]Robert Schöne, Daniel Molka, Michael Werner:
Wake-up latencies for processor idle states on current x86 processors. Comput. Sci. Res. Dev. 30(2): 219-227 (2015) - [c17]Daniel Molka
Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture. ICPP 2015: 739-748 - [c16]Daniel Hackenberg
An Energy Efficiency Feature Survey of the Intel Haswell Processor. IPDPS Workshops 2015: 896-904 - 2014
- [j3]Robert Schöne, Daniel Molka:
Integrating performance analysis and energy efficiency optimizations in a unified environment. Comput. Sci. Res. Dev. 29(3-4): 231-239 (2014) - [c15]Daniel Molka
Main memory and cache performance of intel sandy bridge and AMD bulldozer. MSPC@PLDI 2014: 4:1-4:10 - [c14]Tim Kiefer, Thomas Kissinger, Benjamin Schlegel, Dirk Habich, Daniel Molka, Wolfgang Lehner:
ERIS live: a NUMA-aware in-memory storage engine for tera-scale multiprocessor systems. SIGMOD Conference 2014: 689-692 - [c13]Thomas Kissinger, Tim Kiefer, Benjamin Schlegel, Dirk Habich, Daniel Molka, Wolfgang Lehner:
ERIS: A NUMA-Aware In-Memory Storage Engine for Analytical Workload. ADMS@VLDB 2014: 74-85 - 2013
- [c12]Daniel Hackenberg
Introducing FIRESTARTER: A processor stress test utility. IGCC 2013: 1-9 - [c11]Daniel Hackenberg
Power measurement techniques on standard compute nodes: A quantitative comparison. ISPASS 2013: 194-204 - [c10]Robert Schöne
Potentials and Limitations for Energy Efficiency Auto-Tuning. PARCO 2013: 678-687 - 2012
- [j2]Daniel Molka
Flexible workload generation for HPC cluster efficiency benchmarking. Comput. Sci. Res. Dev. 27(4): 235-243 (2012) - [c9]Matthias S. Müller
SPEC OMP2012 - An Application Benchmark Suite for Parallel Systems Using OpenMP. IWOMP 2012: 223-236 - [c8]Robert Schöne, Daniel Hackenberg, Daniel Molka:
Memory Performance at Reduced CPU Clock Speeds: An Analysis of Current x86_64 Processors. HotPower 2012 - [r1]Timo Minartz, Daniel Molka, Julian M. Kunkel, Michael Knobloch, Michael Kuhn, Thomas Ludwig:
Tool Environments to Measure Power Consumption and Computational Performance. Handbook of Energy-Aware and Green Computing 2012: 709-744 - 2011
- [c7]Daniel Molka
Memory Performance and SPEC OpenMP Scalability on Quad-Socket x86_64 Systems. ICA3PP (1) 2011: 170-181 - [c6]Michael Knobloch, Timo Minartz, Daniel Molka, Stephan Krempel, Thomas Ludwig, Bernd Mohr:
Electronic poster: eeclust: energy-efficient cluster computing. SC Companion 2011: 99-100 - [c5]Robert Schöne
Simultaneous multithreading on x86_64 systems: an energy efficiency evaluation. HotPower@SOSP 2011: 10:1-10:5 - 2010
- [j1]Daniel Hackenberg
Quantifying power consumption variations of HPC systems using SPEC MPI benchmarks. Comput. Sci. Res. Dev. 25(3-4): 155-163 (2010) - [c4]Timo Minartz, Daniel Molka, Michael Knobloch
eeClust: Energy-Efficient Cluster Computing. CHPC 2010: 111-124 - [c3]Daniel Molka
Characterizing the energy consumption of data transfers and arithmetic operations on x86-64 processors. Green Computing Conference 2010: 123-133
2000 – 2009
- 2009
- [c2]Daniel Molka
Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System. PACT 2009: 261-270 - [c1]Daniel Hackenberg
Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems. MICRO 2009: 413-422
Coauthor Index
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