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Tong Lin 0001
Person information
- affiliation: Nanyang Technological University of Singapore, School of Electrical and Electronic Engineering, Singapore
Other persons with the same name
- Tong Lin — disambiguation page
- Tong Lin 0002
— Peking University, School of Intelligence Science and Technology, Beijing, China
- Tong Lin 0003 — State Grid Corporation of China, China
- Tong Lin 0004 — Nanjing University of Science and Technology, China
- Tong Lin 0005 — University of Michigan, MI, USA
- Tong Lin 0006 — National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan
- Tong Lin 0007
- Tong Lin 0008
- Tong Lin 0009 — Carnegie Mellon University, Pittsburgh, PA, USA
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2020 – today
- 2024
- [j8]Yee-Yang Tee
Integrated Circuit Mask-Generative Adversarial Network for Circuit Annotation With Targeted Data Augmentation. IEEE Intell. Syst. 39(1): 37-45 (2024) - [c16]Xuenong Hong, Zilong Hu, Han Zhang, Yee-Yang Tee, Tong Lin, Yiqiong Shi, Deruo Cheng, Bah-Hwee Gwee:
MLConnect: A Machine Learning Based Connection Prediction Framework for Error Correction in Recovered Circuit. ISCAS 2024: 1-5 - 2023
- [j7]Xuenong Hong
GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning. IEEE Trans. Artif. Intell. 4(5): 1199-1213 (2023) - [j6]Yee-Yang Tee
Patch-Based Adversarial Training for Error-Aware Circuit Annotation of Delayered IC Images. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3694-3698 (2023) - [c15]Erdong Huang, Xuenong Hong, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee:
GRACER: Graph-Based Standard Cell Recognition in IC Images for Hardware Assurance. IECON 2023: 1-6 - [c14]Tong Lin, Yiqiong Shi, Bah-Hwee Gwee:
SEM2GDS: A Deep-Learning Based Framework To Detect Malicious Modifications In IC Layout. ISCAS 2023: 1-5 - 2022
- [j5]Deruo Cheng
Delayered IC image analysis with template-based Tanimoto Convolution and Morphological Decision. IET Circuits Devices Syst. 16(2): 169-177 (2022) - [i1]Yee-Yang Tee, Deruo Cheng
Unsupervised Domain Adaptation with Histogram-gated Image Translation for Delayered IC Image Analysis. CoRR abs/2209.13479 (2022) - 2021
- [c13]Ling Huang, Deruo Cheng
Joint Anomaly Detection and Inpainting for Microscopy Images Via Deep Self-Supervised Learning. ICIP 2021: 3497-3501
2010 – 2019
- 2019
- [j4]Deruo Cheng
A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images. IEEE Intell. Syst. 34(2): 36-43 (2019) - [c12]Deruo Cheng
Global Template Projection and Matching Method for Training-Free Analysis of Delayered IC Images. ISCAS 2019: 1-5 - 2018
- [j3]Deruo Cheng
Hybrid K-Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1849-1853 (2018) - [c11]Xuenong Hong, Deruo Cheng
Deep Learning for Automatic IC Image Analysis. DSP 2018: 1-5 - [c10]Ne Kyaw Zwa Lwin, H. Sivaramakrishnan, Kwen-Siong Chong, Tong Lin, Wei Shu, Joseph S. Chang:
Single-Event-Transient Resilient Memory for DSP in Space Applications. DSP 2018: 1-5 - 2017
- [j2]Kwen-Siong Chong, Weng-Geng Ho
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 402-415 (2017) - 2016
- [c9]Jize Jiang, Wei Shu, Kwen-Siong Chong, Tong Lin, Ne Kyaw Zwa Lwin, Joseph Sylvester Chang, Jingyuan Liu:
Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process. ISCAS 2016: 5-8 - [c8]Tong Lin, Kwen-Siong Chong, Wei Shu, Ne Kyaw Zwa Lwin, Jize Jiang, Joseph S. Chang:
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process. ISCAS 2016: 966-969 - 2015
- [c7]Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee
A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. ISCAS 2015: 2589-2592 - 2014
- [c6]Joseph S. Chang, Kwen-Siong Chong, Wei Shu, Tong Lin, Jize Jiang, Ne Kyaw Zwa Lwin, Yang Kang:
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process. MWSCAS 2014: 821-824 - [c5]Tong Ge, Joseph S. Chang, Tong Lin, Lei Zhang, Lim Geok Soon:
Fully-Additive printed electronics on flexible substrates: A Fully-Additive RFID tag. MWSCAS 2014: 825-828 - 2013
- [j1]Tong Lin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks. IEEE J. Solid State Circuits 48(2): 573-586 (2013) - [c4]Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. ISCAS 2013: 3022-3025 - 2012
- [c3]Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. ISCAS 2012: 492-495 - [c2]Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee
A comparative study on asynchronous Quasi-Delay-Insensitive templates. ISCAS 2012: 1819-1822
2000 – 2009
- 2009
- [c1]Tong Lin, Kwen-Siong Chong, Bah-Hwee Gwee
Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic. ISCAS 2009: 3162-3165
Coauthor Index
aka: Joseph S. Chang
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