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Maitham Shams
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2020 – today
- 2023
- [c22]Waqas Gul, Maitham Shams, Dhamin Al-Khalili:
FinFET 6T-SRAM Compute-in-Memory Targeting Low Power Neural Networks Operations. ISCAS 2023: 1-4
2010 – 2019
- 2018
- [j10]Roya Dibaj
, Dhamin Al-Khalili, Maitham Shams:
Gate Oxide Short Defect Model in FinFETs. J. Electron. Test. 34(3): 351-362 (2018) - [c21]Morteza Nabavi, Maitham Shams, Mohamad Sawan:
Temperature Independent Subthreshold Circuits Design. ISOCC 2018: 92-93 - 2017
- [c20]Roya Dibaj, Dhamin Al-Khalili, Maitham Shams:
Comprehensive investigation of gate oxide short in FinFETs. VTS 2017: 1-6 - 2015
- [c19]Sukneet Basuta, Maitham Shams:
Single-ended 6T sub-threshold SRAM with horizontal local bit-lines. MWSCAS 2015: 1-4 - 2014
- [j9]Bashir I. Morshed, Maitham Shams, Tofy Mussivand:
Investigation of Low-Voltage Pulse Parameters on Electroporation and Electrical Lysis Using a Microfluidic Device With Interdigitated Electrodes. IEEE Trans. Biomed. Eng. 61(3): 871-882 (2014) - 2013
- [j8]Bashir I. Morshed, Maitham Shams, Tofy Mussivand:
Analysis of Electric Fields inside Microchannels and Single Cell Electrical Lysis with a Microfluidic Device. Micromachines 4(2): 243-256 (2013) - 2012
- [j7]Muhammad Arsalan
Ultra Low Power CMOS-Based Sensor for On-Body Radiation Dose Measurements. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(1): 34-41 (2012) - [j6]Morteza Nabavi, Maitham Shams:
A gate sizing and transistor fingering strategy for subthreshold CMOS circuits. IEICE Electron. Express 9(19): 1550-1555 (2012) - 2011
- [j5]Bashir I. Morshed, Maitham Shams, Tofy Mussivand:
A simple and effective fluidic encapsulation protocol for bioMEMS devices. IEICE Electron. Express 8(19): 1549-1555 (2011) - [j4]Manmit Muker, Maitham Shams:
Preference of designing CMOS subthreshold logic circuits using uniform-size transistors. IEICE Electron. Express 8(23): 1983-1988 (2011) - 2010
- [j3]Osman Musa Abdulkarim, Maitham Shams:
An Efficient Delay Model for MOS Current-Mode Logic Automated Design and Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8): 2041-2052 (2010)
2000 – 2009
- 2008
- [j2]Atif Shamim, Muhammad Arsalan
Wireless Dosimeter: System-on-Chip Versus System-in-Package for Biomedical and Space Applications. IEEE Trans. Circuits Syst. II Express Briefs 55-II(7): 643-647 (2008) - [c18]Raghid Shreih, Maitham Shams:
Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies. ACM Great Lakes Symposium on VLSI 2008: 189-194 - 2007
- [c17]Osman Musa Abdulkarim, Maitham Shams:
A symmetric mos current-mode logic universal gate for high speed applications. ACM Great Lakes Symposium on VLSI 2007: 212-215 - [c16]Muhammad Arsalan, Maitham Shams:
Asynchronous Adiabatic Logic. ISCAS 2007: 3720-3723 - 2006
- [c15]Ahmad Mizannojehdehi, Maitham Shams, Tofy Mussivand:
Design and Analysis of A Class-E Frequency-Controlled Transcutaneous Energy Transfer System. ICECS 2006: 21-24 - 2005
- [c14]Tin Wai Kwan, Maitham Shams:
Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic. ASYNC 2005: 23-32 - [c13]Shahnam Khabiri, Maitham Shams:
An MCML four-bit ripple-carry adder design in 1 GHz range. ISCAS (2) 2005: 1634-1637 - [c12]Shahnam Khabiri, Maitham Shams:
A mathematical programming approach to designing MOS current-mode logic circuits. ISCAS (3) 2005: 2425-2428 - [c11]Yuanzhong Wan, Maitham Shams:
Delay modeling of CMOS/CPL logic circuits. ISCAS (6) 2005: 5613-5616 - [c10]Muhammad Arsalan, Maitham Shams:
Charge-Recovery Power Clock Generators for Adiabatic Logic Circuits. VLSI Design 2005: 171-174 - [c9]Yuanzhong Wan, Maitham Shams:
Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder. VLSI Design 2005: 261-266 - [c8]Tin Wai Kwan, Maitham Shams:
Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode Logic. VLSI Design 2005: 301-306 - 2004
- [c7]Tin Wai Kwan, Maitham Shams:
Multi-GHz energy-efficient asynchronous pipelined circuits in MOS Current Mode Logic. ISCAS (2) 2004: 645-648 - [c6]Shahnam Khabiri, Maitham Shams:
Implementation of MCML universal logic gate for 10 GHz-range in 0.13 µm CMOS technology. ISCAS (2) 2004: 653-656 - 2003
- [c5]Maitham Shams:
A unified delay model for CMOS logic styles. ICECS 2003: 874-877
1990 – 1999
- 1999
- [c4]Maitham Shams, Mohamed I. Elmasry:
Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions. ICCD 1999: 563-568 - [c3]Maitham Shams, Mohamed I. Elmasry:
A formulation for quick evaluation and optimization of digital CMOS circuits. ISCAS (6) 1999: 326-329 - 1998
- [j1]Maitham Shams, Jo C. Ebergen, Mohamed I. Elmasry:
Modeling and comparing CMOS implementations of the C-element. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 563-567 (1998) - 1997
- [c2]Maitham Shams, Jo C. Ebergen, Mohamed I. Elmasry:
Optimizing CMOS Implementations of the C-element. ICCD 1997: 700-705 - 1996
- [c1]Maitham Shams, Jo C. Ebergen, Mohamed I. Elmasry:
A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element. ISLPED 1996: 93-96
Coauthor Index
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