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Roghayeh Saeidi
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2020 – today
- 2022
- [j13]Léopold Van Brandt
, Roghayeh Saeidi
Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2767-2780 (2022) - [j12]Mohammadreza Pourfard
KAZE-SAR: SAR Image Registration Using KAZE Detector and Modified SURF Descriptor for Tackling Speckle Noise. IEEE Trans. Geosci. Remote. Sens. 60: 1-12 (2022) - 2021
- [j11]Mansoureh Labbafniya, Shahram Etemadi Borujeni, Roghayeh Saeidi
Hardware Trojan Prevention and Detection by Filling Unused Space Using Shift registers, Gate-chain and Extra Routing. ISC Int. J. Inf. Secur. 13(1): 47-57 (2021) - [j10]David Bol
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. IEEE J. Solid State Circuits 56(7): 2256-2269 (2021) - [c11]Rémi Dekimpe, Maxime Schramme, Martin Lefebvre
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management. VLSI Circuits 2021: 1-2 - 2020
- [j9]Ata Khorami, Roghayeh Saeidi
A low-power low-offset charge-sharing technique for double-tail comparators. Microelectron. J. 102: 104842 (2020) - [j8]Ata Khorami, Roghayeh Saeidi
Energy consumption analysis of the stepwise adiabatic circuits. Microelectron. J. 104: 104868 (2020) - [c10]Roghayeh Saeidi
SRAM Security and Vulnerability To Hardware Trojan: Design Considerations. MWSCAS 2020: 722-725
2010 – 2019
- 2019
- [j7]Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi
Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing. Integr. 65: 128-137 (2019) - [j6]Ata Khorami, Roghayeh Saeidi
A low-power dynamic comparator for low-offset applications. Integr. 69: 23-30 (2019) - [j5]Mansoureh Labbafniya, Roghayeh Saeidi:
Secure FPGA Design by Filling Unused Spaces. ISC Int. J. Inf. Secur. 11(1): 47-56 (2019) - [c9]Ata Khorami, Roghayeh Saeidi, Mohammad Sharifkhani, Nima Taherinejad:
An Ultra Low-power Low-offset Double-tail Comparator. NEWCAS 2019: 1-4 - 2018
- [j4]Leila Bagheriye
A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1708-1712 (2018) - [j3]Leila Bagheriye
Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1051-1058 (2018) - [c8]Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi
A Novel Sensing Circuit with Large Sensing Margin for Embedded Spin-Transfer Torque MRAMs. ISCAS 2018: 1-5 - 2016
- [c7]Leila Bagheriye, Roghayeh Saeidi
Low power and roboust FinFET SRAM cell using independent gate control. ISCAS 2016: 49-52 - [c6]Roghayeh Saeidi, Hossein Gharaee Garakani:
SRAM hardware Trojan. IST 2016: 719-722 - 2014
- [j2]Roghayeh Saeidi
A Subthreshold Symmetric SRAM Cell With High Read Stability. IEEE Trans. Circuits Syst. II Express Briefs 61-II(1): 26-30 (2014) - [j1]Roghayeh Saeidi
Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3386-3393 (2014) - 2013
- [c5]Sina Hassanzadeh, Milad Zamani, Khosrow Hajsadeghi, Roghayeh Saeidi:
A novel low power 8T-cell sub-threshold SRAM with improved read-SNM. DTIS 2013: 35-38 - [c4]Milad Zamani, Sina Hassanzadeh, Khosrow Hajsadeghi, Roghayeh Saeidi:
A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM. DTIS 2013: 104-107 - 2011
- [c3]Roghayeh Saeidi
A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria. ISCAS 2011: 61-64
2000 – 2009
- 2006
- [c2]Fatemeh Kalantari, Nasser Masoumi, Nafiseh Gholampour, Roghayeh Saeidi
A 5 GHz CMOS low noise amplifier with a 3.25 turn spiral inductor for IEEE802.16a. WCNC 2006: 2330-2334 - 2005
- [c1]Mahmoud Saeidi, Seyed Ahmad Motamedi, Alireza Behrad, Behzad Saeidi, Roghayeh Saeidi, Reza Saeidi:
Noise reduction of consecutive images using a new adaptive weighted averaging filter. SIP 2005: 214-219
Coauthor Index
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