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Peter Bellows
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2000 – 2009
- 2005
- [j2]Peter Bellows:
High-Visibility Debug-By-Design for FPGA Platforms. J. Supercomput. 32(2): 105-118 (2005) - 2004
- [c8]Peter Bellows:
Distinguished Paper: High-Visibility Debug-by-Design for FPGA Platforms. ERSA 2004: 247-258 - 2003
- [c7]Brian Schott, Peter Bellows, Matthew French, Robert Parker:
Applications of adaptive computing systems for signal processing challenges. ASP-DAC 2003: 465-470 - [c6]Peter Bellows, Jaroslav Flidr, Ladan Gharai, Colin Perkins
, Pawel Chodowiec, Kris Gaj:
IPsec-Protected Transport of HDTV over IP. FPL 2003: 869-879 - 2002
- [c5]Peter Bellows, Jaroslav Flidr, Tom Lehman, Brian Schott, Keith D. Underwood:
GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing. FCCM 2002: 121-130 - [c4]Tim Grembowski, Roar Lien, Kris Gaj, Nghi Nguyen
Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512. ISC 2002: 75-89 - 2001
- [j1]Peter Bellows, Brad L. Hutchings:
Designing Run-Time Reconfigurable Systems with JHDL. J. VLSI Signal Process. 28(1-2): 29-45 (2001) - [c3]Pawel Chodowiec, Kris Gaj, Peter Bellows, Brian Schott:
Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board. ISC 2001: 220-234
1990 – 1999
- 1999
- [c2]Brad L. Hutchings, Peter Bellows, Joseph Hawkins, K. Scott Hemmert, Brent E. Nelson, Mike Rytting:
A CAD Suite for High-Performance FPGA Design. FCCM 1999: 12-24 - 1998
- [c1]Peter Bellows, Brad L. Hutchings:
JHDL - An HDL for Reconfigurable Systems. FCCM 1998: 175-184
Coauthor Index
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