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Kishor Sarawadekar
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2020 – today
- 2024
- [j21]Purnendu Mishra
, Kishor Sarawadekar
Multiple-Hand 2D Pose Estimation From a Monocular RGB Image. IEEE Access 12: 40722-40735 (2024) - [j20]Sumit Kr. Yadav, Kishor Sarawadekar:
Robust multi-scale weighting-based edge-smoothing filter for single image dehazing. Pattern Recognit. 149: 110137 (2024) - [j19]Bharat Bhushan Upadhyay
A Low Cost FPGA Implementation of Retinex Based Low-Light Image Enhancement Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3503-3507 (2024) - 2023
- [j18]Sumit Kr. Yadav, Kishor Sarawadekar
An Effective Scale-Aware Edge-Smoothing Weighting Constraint-Based Weighted Guided Image Filter for Single Image Dehazing. Circuits Syst. Signal Process. 42(10): 6136-6159 (2023) - [j17]Sumit Kr. Yadav, Kishor Sarawadekar:
Effective edge-aware weighting filter-based structural patch decomposition multi-exposure image fusion for single image dehazing. Multidimens. Syst. Signal Process. 34(2): 543-574 (2023) - [j16]Bharat Bhushan Upadhyay
VLSI Design of Saturation-Based Image Dehazing Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 31(7): 959-968 (2023) - [j15]Sumit Kr. Yadav, Kishor Sarawadekar
A New Robust Scale-Aware Weighting-Based Effective Edge-Preserving Gradient Domain Guided Image Filter for Single Image Dehazing. J. Signal Process. Syst. 95(4): 475-493 (2023) - [c17]Vemanaboina Vamsi, Kishor Sarawadekar:
FPGA Implementation of Inversion in Galois Field Over GF(2m) with FLT and ITA Using Quad Blocks. APCCAS 2023: 36-39 - [c16]Bharat Bhushan Upadhyay, Kishor Prabhakar Sarawadekar:
FPGA Implementation of Dehazing Model Based Low-Light Image Enhancement Algorithm. MWSCAS 2023: 836-840 - 2022
- [j14]Purnendu Mishra
Fingertips Detection With Nearest-Neighbor Pose Particles From a Single RGB Image. IEEE Trans. Circuits Syst. Video Technol. 32(5): 3001-3011 (2022) - [j13]Gourav Modanwal
Can Visually Impaired Use Gestures to Interact With Computers? A Cognitive Load Perspective. IEEE Trans. Hum. Mach. Syst. 52(2): 267-275 (2022) - [c15]Bharat Bhushan Upadhyay, Sumit Kr. Yadav, Kishor Prabhakar Sarawadekar:
VLSI Architecture of Saturation Based Image Dehazing Algorithm and its FPGA Implementation. MWSCAS 2022: 1-4 - 2020
- [j12]Subiman Chatterjee
Exploiting Trigonometric Properties to Optimize Higher Order DCT Architecture in HEVC. IEEE Trans. Circuits Syst. Video Technol. 30(10): 3598-3607 (2020) - [c14]Sumit Kr. Yadav, Kishor Sarawadekar:
Steering Kernel-Based Guided Image Filter for Single Image Dehazing. TENCON 2020: 444-449 - [c13]Tanushree Meena
Gender Recognition using in-built Inertial Sensors of Smartphone. TENCON 2020: 462-467 - [i1]Purnendu Mishra, Kishor Sarawadekar:
Anchors Based Method for Fingertips Position Estimation from a Monocular RGB Image using Deep Neural Network. CoRR abs/2005.01351 (2020)
2010 – 2019
- 2019
- [j11]Subiman Chatterjee
WHT and Matrix Decomposition-Based Approximated IDCT Architecture for HEVC. IEEE Trans. Circuits Syst. II Express Briefs 66-II(6): 1043-1047 (2019) - [j10]Subiman Chatterjee
Approximated Core Transform Architectures for HEVC Using WHT-Based Decomposition Method. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4296-4308 (2019) - [c12]Rahul Pal
A Cross Entropy Minimization based Beam Selection for Time-Variant mmWave Beamspace MU-MIMO Communication System. ANTS 2019: 1-5 - [c11]Rahul Pal
Performance Study of mmWave Beamspace MU-MIMO-NOMA Communication System. ANTS 2019: 1-6 - [c10]Purnendu Mishra, Kishor Sarawadekar:
Fingertips Detection in Egocentric Video Frames using Deep Neural Networks. IVCNZ 2019: 1-6 - [c9]Sumit Kr. Yadav, Kishor Sarawadekar:
Single Image Dehazing using Adaptive Gamma Correction Method. TENCON 2019: 1752-1757 - [c8]Purnendu Mishra, Kishor Sarawadekar:
Polynomial Learning Rate Policy with Warm Restart for Deep Neural Network. TENCON 2019: 2087-2092 - 2018
- [j9]Gourav Modanwal
A robust wrist point detection algorithm using geometric features. Pattern Recognit. Lett. 110: 72-78 (2018) - [j8]Subiman Chatterjee
An Optimized Architecture of HEVC Core Transform Using Real-Valued DCT Coefficients. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 2052-2056 (2018) - [j7]Gourav Modanwal
A New Dactylology and Interactive System Development for Blind-Computer Interaction. IEEE Trans. Hum. Mach. Syst. 48(2): 207-212 (2018) - [c7]Gourav Modanwal
A Gesture Elicitation Study with Visually Impaired Users. HCI (29) 2018: 54-61 - [c6]Gourav Modanwal
A Robust Algorithm for Hand-forearm Segmentation. ICIGP 2018: 102-105 - 2016
- [j6]Gourav Modanwal
Towards hand gesture based writing support system for blinds. Pattern Recognit. 57: 50-60 (2016) - [j5]Gourav Modanwal, Kishor Sarawadekar:
Corrigendum to "Towards hand gesture based writing support system for blinds" [Pattern Recognit. Pattern Recognit. 60: 57 (2016) - [c5]Gourav Modanwal
Development of a New Dactylology and Writing Support System Especially for Blinds. CRV 2016: 362-369 - [c4]Subiman Chatterjee, Kishor Prabhakar Sarawadekar:
A low cost, constant throughput and reusable 8#x00D7;8 DCT architecture for HEVC. MWSCAS 2016: 1-4 - [c3]Subiman Chatterjee, Kishor Sarawadekar:
Constant throughput HEVC core transform design. MWSCAS 2016: 1-4 - 2015
- [j4]Rakesh Biswas
An FPGA-based architecture of DSC-SRI units specially for motion blind ultrasound systems. J. Real Time Image Process. 10(3): 573-595 (2015) - 2012
- [j3]Kishor Sarawadekar, Swapna Banerjee:
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000. Integr. 45(1): 1-8 (2012) - [j2]Kishor Sarawadekar, Harihar Bharat Indana, Deep Bera, Swapna Banerjee:
VLSI-DSP based real time solution of DSC-SRI for an ultrasound system. Microprocess. Microsystems 36(1): 1-12 (2012) - 2011
- [j1]Kishor Sarawadekar, Swapna Banerjee:
An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000. IEEE Trans. Circuits Syst. Video Technol. 21(6): 825-836 (2011)
2000 – 2009
- 2009
- [c2]Kishor Sarawadekar, Swapna Banerjee:
A high speed bit plane coder for JPEG 2000 and it's FPGA implementation. EUSIPCO 2009: 2231-2234 - [c1]Kishor Sarawadekar, Swapna Banerjee:
Efficient VLSI architecture for bit plane encoder of JPEG 2000. ICIP 2009: 2805-2808
Coauthor Index
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last updated on 2024-07-20 20:32 CEST by the dblp team
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