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Arjun Rajagopal
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2010 – 2019
- 2012
- [c6]Raguram Damodaran, Timothy Anderson, Sanjive Agarwala, Rama Venkatasubramanian, Michael Gill, Dhileep Gopalakrishnan, Anthony M. Hill, Abhijeet Chachad, Dheera Balasubramanian, Naveen Bhoria, Jonathan Tran, Duc Bui, Mujibur Rahman, Shriram Moharil, Matthew Pierson, Steven Mullinnix, Hung Ong, David Thompson, Krishna Gurram, Oluleye Olorode, Nuruddin Mahmood, Jose Flores, Arjun Rajagopal, Soujanya Narnur, Daniel Wu, Alan Hales, Kyle Peavy, Robert Sussman:
A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS. VLSI Design 2012: 286-291
2000 – 2009
- 2008
- [c5]Anand Rajaram, Raguram Damodaran, Arjun Rajagopal:
Practical Clock Tree Robustness Signoff Metrics. ISQED 2008: 676-679 - 2007
- [c4]Sanjive Agarwala, Arjun Rajagopal, Anthony M. Hill, Mayur Joshi, Steven Mullinnix, Timothy Anderson, Raguram Damodaran, Lewis Nardini, Paul Wiley, Peter Groves, John Apostol, Michael Gill, Jose Flores, Abhijeet Chachad, Alan Hales, Kai Chirca, Krishna Panda, Rama Venkatasubramanian, Patrick Eyres, Rajasekhar Velamuri, Anand Rajaram, Manjeri Krishnan, Jonathan Nelson, Jose Frade, Mujibur Rahman, Nuruddin Mahmood, Usha Narasimha, Snehamay Sinha, Sridhar Krishnan, William Webster, Duc Bui, Shriram Moharil, Neil Common, Rejitha Nair, Rajesh Ramanujam, Monica Ryan:
A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure. ISSCC 2007: 262-601 - 2006
- [c3]Arjun Rajagopal:
Clock tree design challenges for robust and low power design. ISPD 2006: 168 - 2004
- [c2]Sanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony M. Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, N. S. Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich:
A 800 MHz System-on-Chip for Wireless Infrastructure Applications. VLSI Design 2004: 381- - 2002
- [j1]Sanjive Agarwala, Timothy Anderson, Anthony M. Hill, M. D. Ales, Raguram Damodaran, Paul Wiley, Steven Mullinnix, J. Leach, Anthony Lell, Michael Gill, Arjun Rajagopal, Abhijeet Chachad, M. Agarwala, John Apostol, Manjeri Krishnan, Duc Bui, Quang An, N. S. Nagaraj, Tod Wolf, T. T. Elappuparackal:
A 600-MHz VLIW DSP. IEEE J. Solid State Circuits 37(11): 1532-1544 (2002)
1990 – 1999
- 1993
- [c1]Arjun Rajagopal, Belli Kuttanna, Balaji Janakiraman, Rajarshi Mukherjee, Joy Shetler:
A Reconfigurable Arithmetic Processor. VLSI Design 1993: 172-175
Coauthor Index
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